DS90C3201

FPD-Link

Transmitter

Video

Source

Pixel Data

DE

Clock

VSYNC

HSYNC

Host

(PC, Graphics Board, Video Processor)

Display

(LCD Monitor, LCD TV, Digital TV)

DS90C3202

FPD-Link

Receiver

Digital

Display

Pixel Data

DE

Clock

VSYNC

HSYNC

LVDS Clock

5 Pairs

5 Pairs

LVDS

2-Wire Serial

Interface

PLL

7

7

7

7

7

7

7

7

7

7

RFB

PWDNB

TCLKIN

TXOA [6:0]

TXOB[6:0]

TXOC [6:0]

TXOD [6:0]

TXOE[6:0]

TXEA[6:0]

TXEB[6:0]

TXEC[6:0]

TXED[6:0]

TXEE[6:0]

S2CLK

S2DAT

TXOA-/+

TXOB-/+

TXOC-/+

TXOD-/+

TXOE-/+

TXEA -/+

TXEB -/+

TXEC-/+

TXED-/+

TXEE -/+

TCLKOUT -/+

MODE0

MODE1

DS90C3201

SNLS192D – APRIL 2005 – REVISED APRIL 2013

www.ti.com

Block Diagram

Figure 1. Transmitter Block Diagram

Typical Application Diagram

Figure 2. LCD Panel Application Diagram

Functional Description

The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Receiver FPD-Link chipset designed to

transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface

between the digital video processor and the display using a LVDS interface. The DS90C3201 transmitter

serializes 2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals

(HSYNC, VSYNC, DE and two user-defined signals) along with clock signal to 10 channels of LVDS signals and

transmits them. The DS90C3202 receiver converts 10 channels of LVDS signals into parallel signals and outputs

2

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