Pin #

TTL LEVEL LOGIC OUTPUTS

21

SYNCHRONIZED DATA (SD): A reconstructed replica of the ENCODED READ DATA signal,

time-stabilized and synchronized to the SYNCHRONIZED CLOCK output.

22

PUMP UP (PU): Active HIGH whenever the phase comparator issues a pump-up signal to the charge

pump. The PU pin is an open-emitter output requiring an external passive pull down resistor whenever in

active use. The output should be allowed to float when not needed.

23

PUMP DOWN (PD): Active HIGH whenever the phase comparator issues a pump-down signal to the

charge pump. The PD pin is an open-emitter output requiring an external passive pull down resistor

whenever in active use. The output should be allowed to float when not needed.

ANALOG SIGNAL PINS

28

CHARGE PUMP OUTPUT: The output of the high-speed, switching bi-directional current source circuitry of

the charge pump. The external, passive PLL filter network is established between this pin, the VCO INPUT

pin, and ground.

1

VCO INPUT: The high-impedance control voltage input to the voltage controlled oscillator (VCO). The

external, passive PLL filter network is established between this pin, the CHARGE PUMP OUTPUT pin, and

ground.

2

TIMING EXTRACTOR FILTER: A pin for the connection of external, passive components employed to

stabilize the delay line timing extraction circuitry. Delay accuracy is not a function of external component

values or tolerances.

25

R

The current is internally multiplied by 2 for charge pump use.

26

R

R

inactive (logical-zero); thus the sum of the resistor currents sets the total input current. The input current is

multiplied by 2 within the charge pump circuitry.

Note 1: These pins should always be tied together; they are not intended to be used with separate power supplies.

2.0 Circuit Operation

In the non-Read mode, the DP8459 PLL is locked to the

REFERENCE CLOCK signal. This permits the VCO to remain

at a frequency very close to the encoded data clock rate while

the PLL is “idling” and thus will minimize the frequency step

and associated lock time encountered at the initiation of lock to

ENCODED READ DATA. Frequency acquisition is employed

in the non-Read mode to ensure lock.

Note: The REFERENCE CLOCK signal is employed by circuitry which sets the

time delay of the internal delay line. This requires the REFERENCE CLOCK

signal to be present

at all times at a stable and accurate frequency for proper

DP8459 operation.

At the assertion of READ GATE, which is allowed to be done

asynchronously (no timing requirements), and following the

completion of two subsequent VCO cycles, the DP8459 VCO

is stopped momentarily and restarted in accurate phase

alignment with the second data bit which arrives following the

VCO pause. This minimization of phase misalignment

between the ENCODED READ DATA and the VCO (referred to

as zero phase start, or ZPS) significantly reduces data lock

acquisition time.

The DP8459 incorporates a preamble-specific frequency

acquisition feature which may be employed at the user’s

option.

The

frequency

acquisition

feature

is

intended

specifically for use within hard or pseudo-hard sectored

systems where READ GATE is asserted only within a

preamble. With the READ GATE active (logical-one) and the

FREQUENCY LOCK CONTROL

(FLC)

input

active

(logical-zero), the DP8459 will be forced to lock to the exact

preamble frequency selected at the SYNC PATTERN SELECT

inputs. The frequency discriminating action of the PLL

provided in this mode produces a lock-in range equivalent to

the available VCO operating range and thus eliminates the

possibility of fractional-harmonic lock. Windowing (pulse gate

action; see Pulse Gate, Section 2.1) is not employed in the

frequency acquisition mode and thus quadrature lock is

prevented (see National Semiconductor Application Note

AN-414, APPS Mass Storage Handbook #1, 1986, for an

explanation of typical false lock modes). The DP8459 will

remain in the frequency acquisition mode until the FLC input is

deactivated (logical-one). In ordinary hard sectored or

pseudo-hard sectored operation, the PREAMBLE DETECTED

(PDT) output is tied to the FLC input for automatic switching

from frequency acquisition to phase lock following internal

detection of the selected preamble by the DP8459. The

Customer may choose to intervene in this path and extend the

frequency lock period. However, the DP8459

must be placed

in the phase lock mode (FLC deactivated—logical-one) prior

to encountering the end of the preamble, or loss of lock will

result.

Switching

of

the

FLC

input

may

be

done

asynchronously (no set-up or hold timing requirements).

The PREAMBLE DETECTED (PDT) output will become active

(logical-one) following READ GATE assertion, completion of

the

ZPS

sequence

and

the

subsequent

detection

of

approximately 32 ENCODED READ DATA (ERD) pulses of the

1T, 2T or 3T preamble types, or 16 ENCODED READ DATA

(ERD) pulses of the 4T preamble type (see specification

tables), and will remain active (logical-one) until deassertion of

READ GATE.

The Customer has the option of employing an elevated PLL

bandwidth during preamble acquisition (or at any other time)

for an extended capture range. An R

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PrintDate=1996/07/31 PrintTime=11:05:41 ds009322 Rev. No. 1

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