DP8459 datasheet(13/35 Pages) NSC

13 / 35 page

FIGURE 12.

FIGURE 13. Control Register

FIGURE 14. Microwire Compatible Control Register Serial Load Timing Diagram

SYNCHRONIZATION FIELD MATCHING DIVIDER

The Synchronization ﬁeld Matching Divider is a programmable

modulus counter employed for implementation of the preamble

frequency lock function. It is placed in the VCO feedback path

to match the relative frequency of the VCO seen at the Phase

Comparator to the frequency of the ENCODED READ DATA

(preamble)

during

the

read

operation

whenever

the

FREQUENCY LOCK CONTROL input is active (logic-zero).

The modulus of the divider, M, is determined by the states of

the SYNC PATTERN SELECT 0 and 1 inputs, as deﬁned by

the table in

Figure 15 .

FIGURE 15. SYNC PATTERN SELECT Input Truth Table

Prior to the assertion of READ GATE, the divider is held in a

known count state and is enabled at the end of the zero phase

TL/F/9322-1

TL/F/9322-15

TL/F/9322-10

Sync Pattern

Sync Matching

Expected

Code

Select

Divider Modulus

Preamble

GCR

MFM; 1,N

2,7

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PrintDate=1996/07/31 PrintTime=11:05:52 ds009322 Rev. No. 1

Proof

DP8459 Datasheet(PDF) 13 Page - National Semiconductor (TI)