DP8459 datasheet(22/35 Pages) NSC

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combination R

NOM ||RBOOST must be equal to or greater than

1.2 k

Ω as per speciﬁcation. Note that in the equation for C

above, the capacitor value is inversely proportional to R

Thus, external ﬁeld interference immunity can be achieved if

1 is maximized through the minimizing of Rp. The selection of

NOM = RBOOST = 2.4 kΩ satisﬁes the requirements for the

Charge Pump resistors and the gain ratio. R

p will be equal to

NOM with READ GATE high, and thus

1 = [1.2x5x20 MHz/(2 x 2.4k x 4)]/(400 Kr/s)

= 0.039 µF

1 can now be calculated:

A standard value of 100

Ω is chosen. Since C

2 ≤ 0.1xC1,C2

will be chosen to be 510 pF. A table listing the dynamics of the

PLL under standard operation conditions and with component

values adjusted to industry standards is shown in

Figure 20 .

FIGURE 20. 2,7 Code, 10 Mbits/Sec Design Example PLL Dynamics

4.0 Window Margin and Bit Jitter Tolerance

A key performance speciﬁcation for the DP8459 involves the

integrity of the synchronization window. The synchronization

window is deﬁned as a continuously repeating time cell,

nominally equal in span to the period of the VCO, within which

an ENCODED READ DATA pulse will be recognized

(captured) regardless of its position within the window (see

Figure 21 ). The captured ERD bit is then transmitted to the

SYNCHRONIZED DATA output on the next occurring SYNC

CLOCK negative edge. The SYNCHRONIZED DATA and the

SYNC CLOCK are held in a ﬁxed, speciﬁed timing relationship

for use by the data controller in deserialization and decoding.

The synchronization window (with strobe setting at nominal

position) is centered about the mean location of the ERD

pulses via the delay line and the time-averaging action of the

PLL. National Semiconductor speciﬁes the static window

truncation (t

of the DP8459 data synchronizer as the

maximum expected loss of the synchronization window seen

adjacent to the ideal window boundary following complete PLL

stabilization with the strobe control setting at the M = −2

position (see

Figure 22 ). Static lock conditions are deﬁned as

having been achieved when the PLL has been allowed to

establish fully stabilized lock to a consistent preamble-type

pattern of nominally positioned, non-shifted ERD pulses.

FIGURE 21. Synchronization Window

Field

Preamble

Min Freq Data

Max Freq Data

Ref Clock

CP Gain

Low

High

Natural

Freq.

400 Krad/s

283 Krad/s

462 Krad/s

800 Krad/s

Damping

Ratio

0.7

0.5

0.8

1.4

TL/F/9322-22

PrintDate=1996/07/31 PrintTime=11:06:08 ds009322 Rev. No. 1

Proof

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