The Delay Line thus remains insensitive to the external

components associated with the extractor as well as to supply

voltage, temperature, and IC process variations.

TIMING EXTRACTOR

This block extracts timing information from the REFERENCE

CLOCK input for use by the variable silicon delay line. External

passive components (tied to the Timing Extractor Filter pin) are

associated with this block, although the accuracy of the

circuit’s function remains independent of the general value and

tolerance of the components. The resistor-capacitor net is

employed

by

the

Timing

Extractor

for

stabilization

purposes—no monostable multivibrator (one-shot) circuitry is

employed by the DP8459. Note that the performance of the

delay line is directly dependent upon the accuracy of the

REFERENCE CLOCK input waveform. Either a crystal

reference generator or a stable servo clock source must be

applied to this input. Multiplexing of the REFERENCE CLOCK

waveform between read operations (within multiple data rate

systems) is acceptable, although sufficient Timing Extractor

stabilization time must be allowed following any perturbation at

this pin before a read operation may be performed (see

Figure

10 for timing table).

PHASE COMPARATOR

The

DP8459

employs

a

digital

Phase

Comparator

(non-harmonic discriminator circuit) which has the capability of

forcing the frequency of the PLL VCO toward the frequency of

the reference input regardless of the magnitude of the

frequency difference. The function of the Phase Comparator

circuit can be represented in a diagrammatically simplified

form as in

Figure 11 .

The Phase Comparator’s action can be disabled at any time

(cleared) via the COAST input pin, allowing the VCO to

free-run.

CHARGE PUMP

The Charge pump is a high speed, switching, dual-gain,

bi-directional current source whose current flow is controlled

by the digital Phase Comparator circuit. The current pulses at

the CHARGE PUMP OUTPUT (CPO) pin thus reflect the

magnitude and sign of the phase error seen at the input of the

Phase Comparator. The CPO pin is connected externally to a

passive component network whose impedance translates the

aggregate current into a voltage for the VCO INPUT while

providing a low-pass filter function for the PLL. The matched

source and sink current generators’ operating currents are set

via the R

from V

R

into each of these pins is internally multiplied by 2 for Charge

Pump use. The CPO current is defined as follows:

I

HIGH GAIN DISABLE high (logical-one)

I

HIGH GAIN DISABLE low (logical-zero)

FIGURE 10. TIMING EXTRACTOR FILTER Component Values for Various Data Rates

FIGURE 11. Simplified Digital Phase-Frequency Comparator

VOLTAGE CONTROL OSCILLATOR (VCO)

The DP8459 VCO is comprised of two portions—a self

contained, high frequency oscillator (no external components)

whose frequency is regulated by the voltage at the VCO

INPUT pin, and a programmable modulus digital divider. The

oscillator is only required to operate over approximately a 2:1

frequency range; the divider modulus is programmable in

factors of 2. The two blocks work in conjunction to achieve a

continuous range of equivalent VCO operating frequencies

from 500 kHz to 50 MHz. (See

Figure 12. )

CONTROL REGISTER

Within the DP8459, the Control Register is a MICROWIRE

compatible, 6-bit shift register block with bits 0 through 4

employed to control the window strobe function and bit 5

employed to regulate the device test mode (see

Figures 13

and

14 ). Information is serially shifted into the Control

Register via the CRD and CRC (negative edge clock) pins

whenever the CRE pin is active (logical-zero). When the CRE

pin is inactive (logical-one), CRD and CRC are ignored.

Figure 3 shows the truth table for the VCO range select

function;

Figure 4 shows the truth table for the window strobe

function.

RFC Frequency

1

4

10

20

40

MHz

CT1

0.82

0.2

0.082

0.056

0.027

µF

RT1

68

68

68

68

68

Ω

Settling Time

192

96

19.2

9.6

4.6

µs

Values may be interpolated for intermediate data rates. Timing Extractor settling times are given which indicate time required for the DP8459 to accommodate a

change of Strobe setting from nominal selection to either extreme (early/late), or vice versa, to within approximately 1% of final value.

TL/F/9322-17

PrintDate=1996/07/31 PrintTime=11:05:51 ds009322 Rev. No. 1

Proof

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