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DP8459 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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DP8459 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 35 page  FIGURE 4. Window Strobe Truth Table Customers who employ the DP8459 in a system without a MICROWIRE™ (or functionally equivalent) bus configuration and who wish to fix the synchronization window in the nominal position while deselecting the test mode need only load all-zero’s into the Control Register following power-up; this may be easily achieved in some system configurations (requiring no additional hardware) by tying CRE to RG, tying CRC to ERD and tying CRD to ground, providing the necessary waveforms are present for register loading prior to the first read operation. The DP8459 provides two pins for PLL filtering purposes, CHARGE PUMP OUTPUT (CPO) and VCO INPUT (VCOI). These provide the Customer with great flexibility in fliter design, permitting high-order filter functions for optimization of PLL lock characteristics and bit jitter rejection. For basic 3rd order applications, CPO and VCOI may be tied together (single-node) with a simple lead-lag, C||(R+C) filter tied between these pins and ground. More esoteric filter designs may be implemented if the pins are electrically separated and a two-port filter network is established between CPO, VCOI, and ground. National Semiconductor supplies initial PLL filter recommendations for the single-node configuration within this data sheet with the qualifying statement that they are very general in nature, intended primarily for production testing of static window margin, and are NOT optimized for any particular disk system. For optimum performance, the Customer should pursue a filter design which is individualized and tailored to the requirements of the specific system involved. This is particularly true for the two-port filtering technique. See Figure 5 for initial single-node filter design recommendations. Strobe Bit Strobe Window Strobe 43210 Word M T S (Typical) 01111 −15 −0.270 x τ VCO 01110 −14 −0.252 x τ VCO 01101 −13 −0.234 x τ VCO 01100 −12 −0.216 x τ VCO 01011 −11 −0.198 x τ VCO 01010 −10 −0.180 x τ VCO 01001 −9 −0.162 x τ VCO 01000 −8 −0.144 x τ VCO 00111 −7 −0.126 x τ VCO 00110 −6 −0.108 x τ VCO 00101 −5 −0.090 x τ VCO 00100 −4 −0.072 x τ VCO 00011 −3 −0.054 x τ VCO 00010 −2 −0.036 x τ VCO 00001 −1 −0.018 x τ VCO 00000 0 0 10000 0 0 10001 1 0.018 x τ VCO 10010 2 0.036 x τ VCO 10011 3 0.054 x τ VCO 10100 4 0.072 x τ VCO 10101 5 0.090 x τ VCO 10110 6 0.108 x τ VCO 10111 7 0.126 x τ VCO 11000 8 0.144 x τ VCO 11001 9 0.162 x τ VCO 11010 10 0.180 x τ VCO 11011 11 0.198 x τ VCO 11100 12 0.216 x τ VCO 11101 13 0.234 x τ VCO 11110 14 0.252 x τ VCO 11111 15 0.270 x τ VCO PrintDate=1996/07/31 PrintTime=11:05:47 ds009322 Rev. No. 1 Proof 8 8 http:\\www.national.com |
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