TAS3108IADCPRG4 datasheet(19/63 Pages) TI1

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Clock Controls

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

Clock management for the TAS3108/TAS3108IA consists of two control structures:

• Master clock management

–

Oversees the selection of the clock frequencies for the 8051 microprocessor, the I2C controller, and

the audio DSP core

–

The master clock (MCLKI or XTALI) is the source for these clocks.

–

In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the

DPLL output drives the microprocessor and audio DSP clocks.

–

Also available is the DPLL bypass mode, in which the high-speed master clock directly drives the

microprocessor and audio DSP clocks.

• Serial audio port (SAP) clock management

–

Oversees SAP master/slave mode

–

Controls output of SCLKOUT1, SCLKOUT2, and LRCLK in the SAP master mode

Figure 5-2 shows the clock circuitry in the TAS3108/TAS3108IA. Input pin MCLKI or XTALI provides the

master clock for the TAS3108/TAS3108IA. Within the TAS3108/TAS3108IA, these two inputs are

combined by an OR gate and, thus, only one of these two sources can be active at any one time. The

source that is not active must be logic 0.

In normal operation, 1, 2, or 4 (as determined by the logic levels set at input pins PLL0 and PLL1) divides

the master clock. The DPLL then multiplies this signal by 11 in frequency (PLL2 = LOW). The multiplier

ratio is always 11 (pin PLL2 = LOW). The DPLL output is the processing clock used by the audio DSP

core.

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Clock Controls

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TAS3108IADCPRG4 Datasheet(PDF) 19 Page - Texas Instruments