TAS3108IADCPRG4 datasheet(30/63 Pages) TI1

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TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

Table 6-2. Master Addresses

BASE ADDRESS

CS0

R/W

MASTER ADDRESS

1010 00

0xA0

1010 00

0xA1

1010 00

0xA2

1010 00

0xA3

The following is an example use of the I2C master address to access an external EEPROM. The

TAS3108/TAS3108IA can address up to two EEPROMs depending on the state of CS0. Initially, the

TAS3108/TAS3108IA comes up in I2C master mode. If it finds a memory such as the 24C512 EEPROM, it

reads the headers and data as previously described. In this I2C master mode, the TAS3108/TAS3108IA

addresses the EEPROMs as shown in Table 6-3 and Table 6-4.

Table 6-3. EEPROM Address I2C TAS3108/TAS3108IA Master Mode = 0xA1/A0

MSB

CS0

R/W

(EEPROM)

1/0

Table 6-4. EEPROM Address I2C TAS3108/TAS3108IA Master Mode = 0xA3/A2

MSB

CS0

R/W

(EEPROM)

1/0

Random I2C Transactions

Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. For

random I2C read commands, the TAS3108/TAS3108IA responds with data, a byte at a time, starting at the

subaddress assigned, as long as the master device continues to respond with acknowledges. If a given

subaddress does not use all 32 bits, the unused bits are read as logic 0. I2C write commands, however,

are treated in accordance with the data assignment for that address space. If a write command is received

for a biquad subaddress, for example, the TAS3108/TAS3108IA expects to see five 32-bit words. If fewer

than five data words have been received when a stop command (or another start command) is received,

the data received is discarded.

Sequential I2C Transactions

The TAS3108/TAS3108IA also supports sequential I2C addressing. For write transactions, if a subaddress

is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write

transaction has taken place, and the data for all 16 subaddresses is successfully received by the

TAS3108/TAS3108IA. For I2C sequential write transactions, the subaddress then serves as the start

address, and the amount of data subsequently transmitted before a stop or start is transmitted determines

how many subaddresses are written to. As was true for random addressing, sequential addressing

requires that a complete set of data be transmitted. If only a partial set of data is written to the last

subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; just

the incomplete data is discarded.

Sequential read transactions do not have restrictions on outputting only complete subaddress data sets.

If the master does not issue enough data-received acknowledges to receive all the data for a given

subaddress, the master device does not receive all the data.

If the master device issues more data-received acknowledges than required to receive the data for a given

subaddress, the master device simply receives complete or partial sets of data, depending on how many

data-received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both

sequential and random, can impose wait states.

Microprocessor Controller

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