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TAS3108IADCPRG4 Datasheet(PDF) 25 Page - Texas Instruments |
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TAS3108IADCPRG4 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 63 page ![]() www.ti.com TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 Table 5-4. TAS3108/TAS3108IA MCLK and LRCLK Common Values (MCLK = 12.288 MHz or MCLK = 11.2896 MHz) Input LRCLK fS PLL fS MCLK/ MCLK/ SCLK SCLK Divider Ch SCLKIN SCLKIN X Mux 1, 2, Rate 32, Multi- fDSPCLK Sample LRCLK MCLK Freq SCLK 1, OUT1 Ch per OUT2 1, 2, 4 per Rate Freq 3, 4, 6, 8, 64, 128, plier (MHz) Max fDSPCLK/fS Rate Ratio (MHz) 2, 3, 4, 6, Rate SDOUT Rate (pins SDIN ( × f S) (MHz) 16, 32 192, 256, 11 (pin 135.2 MHz (kHz) ( × f S) 8, 16, 32 ( × f S) ( × f S) PLL0, 384, 512 PLL2) PLL1) Slave Mode, 2 Channels In, 2 Channels Out 32 2 384 12.288 64 2.048 N/A 1 64 2 64 64 1 11 135.2 4224 44.1 2 256 11.2896 64 2.822 N/A 1 64 2 64 64 1 11 124.2 2816 48 2 256 12.288 64 3.072 N/A 1 64 2 64 64 1 11 135.2 2816 88.2 2 128 11.2896 64 5.645 N/A 1 64 2 64 64 1 11 124.2 1408 96 2 128 12.288 64 6.144 N/A 1 64 2 64 64 1 11 135.2 1408 176.4 2 64 11.2896 64 11.290 N/A 1 64 2 64 64 1 11 124.2 704 192 2 64 12.288 64 12.288 N/A 1 64 2 64 64 1 11 135.2 704 Slave Mode, 2 Channels In, TDM Out 44.1 2 256 11.2896 256 11.290 N/A 4 64 8 256 64 1 11 124.2 2816 48 2 256 12.288 256 12.288 N/A 4 64 8 256 64 1 11 135.2 2816 88.2 2 128 11.2896 128 11.290 N/A 2 64 4 128 64 1 11 124.2 1408 96 2 128 12.288 128 6.144 N/A 2 64 4 128 64 1 11 135.2 1408 Slave Mode, TDM In, 2 Channels Out 44.1 8 256 11.2896 256 11.290 N/A 4 256 2 64 64 1 11 124.2 2816 48 8 256 12.288 256 12.288 N/A 4 256 2 64 64 1 11 135.2 2816 88.2 4 128 11.2896 128 11.290 N/A 2 128 2 64 64 1 11 124.2 1408 96 4 128 12.288 128 12.288 N/A 2 128 2 64 64 1 11 135.2 1408 Slave Mode, TDM In, TDM Out 44.1 8 256 11.2896 256 11.290 N/A 1 256 8 256 256 1 11 124.2 2816 48 8 256 12.288 256 12.288 N/A 1 256 8 256 256 1 11 135.2 2816 88.2 4 128 11.2896 128 11.290 N/A 1 128 4 128 128 1 11 124.2 1408 96 4 128 12.288 128 12.288 N/A 1 128 4 128 128 1 11 135.2 1408 Master Mode, 2 Channels In, 2 Channels Out 32 2 384 12.288 N/A N/A 6 1 64 2 64 64 1 11 135.2 4224 44.1 2 256 11.2896 N/A N/A 4 1 64 2 64 64 1 11 124.2 2816 48 2 256 12.288 N/A N/A 4 1 64 2 64 64 1 11 135.2 2816 88.2 2 128 11.2896 N/A N/A 2 1 64 2 64 64 1 11 124.2 1408 96 2 128 12.288 N/A N/A 2 1 64 2 64 64 1 11 135.2 1408 176.4 2 64 11.2896 N/A N/A 1 1 64 2 64 64 1 11 124.2 704 Submit Documentation Feedback Clock Controls 25 Not Recommended for New Designs |
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