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TAS3108IADCPRG4 Datasheet(PDF) 38 Page - Texas Instruments

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Part # TAS3108IADCPRG4
Description  AUDIO DIGITAL SIGNAL PROCESSORS
PDF  63 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TAS3108IADCPRG4 Datasheet(HTML) 38 Page - Texas Instruments

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7.1 Clock Control Register (0x00)
7.1.1
Master Clock Output Divider
TAS3108, TAS3108IA
AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007
Register 0x00 provides the user with control over MCLK, LRCLK, SCLKOUT1, SCLKOUT2, data-word
size, and serial audio port modes. Register 0x00 default = 0x0100 1B22.
Table 7-1. Clock Control Register (0x00)
D31
D30
D29
D28
D27
D26
D25
D24
DESCRIPTION
0
0
0
Not Used
W1
W0
Master clock output divider
Y2
Y1
Y0
Master mode LRCLK divider
D23
D22
D21
D20
D19
D18
D17
D16
DESCRIPTION
ICS
SCLKOUT select (default = 0)
IMS
SAP master/slave mux select (1 = master mode, 0 = slave mode)
X2
X1
X0
SCLKIN and SCLKOUT clock divide
Z2
Z1
Z0
MCLK, SCLK ratio (master mode only)
D15
D14
D13
D12
D11
D10
D9
D8
DESCRIPTION
X
X
Don't care
X
Don't care
IW1
IW0
Input audio data word size
X
Don't care
OW1
OW0
Output audio data word size
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
IM3
IM2
IM1
IM0
Input data format
OM3
OM2
OM1
OM0
Output data format
Bits 28–27 (W1 and W0) define the ratio between MCLKI (or the crystal frequency) and MCLKO. This
allows the accommodation of devices that require an MCLK = 128 LRCLK and devices that require an
MCLK = 256 LRCLK, without having to use glue logic to divide that clock down. This bit has meaning
whether in clock-master or clock-slave mode.
W1
W0
DESCRIPTION
0
0
MCLKO = MCLKI
0
1
MCLKO = MCLKI/2
1
0
MCLKO = MCLKI/4
1
1
MCLKO = MCLKI/4
38
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I2C Register Map
Not Recommended for New Designs



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