TAS3108IADCPRG4 datasheet(24/63 Pages) TI1

24 / 63 page

www.ti.com

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

When the serial audio port (SAP) is in the master mode, the SAP uses the MCLKI or XTALI master clock

to drive the serial port clocks SCLKOUT1, SLCKOUT2, and LRCLK. When the SAP is in the slave mode,

LRCLK is an input and SCLKOUT2 and SCLKOUT1 are derived from SCLKIN. As shown in Figure 5-2,

SCLKOUT1 clocks data into the input SAP and SCLKOUT2 clocks data from the output SAP. Two distinct

clocks are required to support TDM-to-discrete and discrete-to-TDM data-format conversions. Such format

conversions also require that SCLKIN be the higher-valued bit-clock frequency. For TDM-in/discrete-out

format conversions, SCLKIN must be equal to the input bit clock. For discrete-in/TDM-out format

conversions, SCLKIN must be equal to the output bit clock. The frequency settings for SCLKOUT1,

SCLKOUT2, and LRCLK in the SAP master mode, as well as the SAP master/slave mode selection, are

all controlled by I2C commands. Table 5-3 lists the default settings at power turnon or after a received

reset.

Table 5-3. TAS3108/TAS3108IA Clock Default Settings

CLOCK

DEFAULT SETTING

SCLKOUT1

SCLKIN

SCLKOUT2

SCLKIN

MCLKO

MCLKI or XTALI

LRCLK

Input

Audio DSP clock

Set by pins PLL0 and PLL1

Microprocessor clock

Set by pin MICROCLK_DIV

PLL multiply ratio

I2C sampling clock

N = 0

I2C master SCL

M = 8

The selections provided by the dedicated TAS3108/TAS3108IA input pins and the programmable settings

provided by I2C subaddress commands give the TAS3108/TAS3108IA a variety of clocking options.

However, the following clocking restrictions must be adhered to:

• MCLKI or XTALI ≥128 f

NOTE

For some TDM modes, MCLKI or XTALI must be

≥256 f

• Audio DSP clock <136 MHz

• Microprocessor clock/20 ≥ I2C SCL clock

• Microprocessor clock ≤34 MHz

• I2C oversample clock/20 ≥ I2C SCL clock

• XTALI ≤20 MHz

• MCLKI ≤25 MHz

As long as these restrictions are met, all other clocking options are allowed.

See Section 7.1 for information on programming the clock register.

Clock Controls

Submit Documentation Feedback

Not Recommended for New Designs

TAS3108IADCPRG4 Datasheet(PDF) 24 Page - Texas Instruments

TAS3108IADCPRG4 Datasheet(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL