TAS3108IADCPRG4 datasheet(42/63 Pages) TI1

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7.3 I

2C Memory Load Control and Data Registers (0x04 and 0x05)

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

Registers 0x04 (Table 7-3) and 0x05 (Table 7-4) allow the user to download TAS3108/TAS3108IA

program code and data directly from the system I2C controller. This mode is called the I2C slave mode

(from the TAS3108/TAS3108IA point-of-view). See the TAS3108/TAS3108IA Firmware Programmer's

Guide (SLEU067) for more details.

Table 7-3. TAS3108/TAS3108IA Memory Load Control Register (0x04)

BYTE

DATA BLOCK FORMAT

SIZE

NOTES

1–2

Checksum code

2 bytes

Checksum of bytes 2 through N + 8. If this is a termination header,

this value is 0000.

3–4

Memory to be loaded

2 bytes

0 Microprocessor program memory

1 Microprocessor external data memory

2 Audio DSP core program memory

3 Audio DSP core coefficient memory

4 Audio DSP core data memory

5–15 Reserved for future expansion

Unused

1 byte

Reserved for future expansion

6–7

Starting TAS3108/TAS3108IA memory

2 bytes

If this is a termination header – this value is 0000.

address

7–8

Number of data bytes to be transferred

2 bytes

If this is a termination header – this value is 0000.

Table 7-4. TAS3108/TAS3108IA Memory Load Data Register (0x05)

BYTE

8-BIT DATA

28-BIT DATA

48-BIT DATA

54-BIT DATA

Datum 1 D7–D0

0000 D27–D24

0000 0000

Datum 2 D7–D0

D7–D0

0000 0000

00 D53–D48

Datum 3 D7–D0

D15–D8

D47–D40

Datum 4 D7–D0

D7–D0

D39–D32

Datum 5 D7–D0

0000 D27–D24

D31–D24

Datum 6 D7–D0

D23–D16

Datum 7 D7–D0

D15–D8

Datum 8 D7–D0

D7–D0

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I2C Register Map

Not Recommended for New Designs

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