UCD3138128APFC datasheet(19/83 Pages) TI1

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DPWM

ADC12

Front-end Peak Current

Mode

Timer

Filter

Constant

Power/Constant

Current

SPI

DTC

Module

Control

I2C

GIO

RTC

5.31

0.02

2.50

0.21

0.35

0.36

0.12

0.33

0.20

0.07

0.05

0.52

UCD3138128A

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SLUSC99 – JULY 2016

Product Folder Links: UCD3138128A

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tPOR –

The time delay from when VGH is exceeded to when the device comes out of reset.

Brown

Out –

This is the V33A voltage threshold at which the device sets the brown out status bit. In addition an

interrupt can be triggered if enabled.

8.1 Typical Clock Gating Power Savings

The CLKGATECTRL register provides control bits that can enable or disable the clock to several peripherals

such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.

By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in

order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current

consumption of the device. The power savings chart displays the power savings per module. For example there

are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved.

UCD3138128APFC Datasheet(PDF) 19 Page - Texas Instruments

UCD3138128APFC Datasheet(HTML) 19 Page - Texas Instruments

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