UCD3138128APFC datasheet(20/83 Pages) TI1

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UCD3138128A

SLUSC99 – JULY 2016

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9 Detailed Description

9.1 Overview

The UCD3138xA family is a digital power supply controller from Texas Instruments offering superior levels of

integration and performance in a single chip solution. The UCD3138128A, in comparison to Texas Instruments

UCD3138A digital power controller offers 128 kB of program Flash memory. The flexible nature of the

UCD3138xA family makes it suitable for a wide variety of power conversion applications.

In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance

of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and network

infrastructure space. The UCD3138xA family is a fully programmable solution offering customers complete

control of their application, along with ample ability to differentiate their solution. At the same time, TI is

committed to simplifying our customer’s development effort through offering best in class development tools,

including application firmware, Code Composer Studio™ software development environment, and TI’s Fusion

Power Development GUI which enables customers to configure and monitor key system parameters.

9.1.1 ARM Processor

The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit

microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where

two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The

Thumb instructions allow for higher code density equivalent to a 16-bit microprocessor, with the performance of

the 32-bit microprocessor.

The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocks in

the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter.

9.1.2 Memory

The UCD3138xA (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of

the memory modules. All of the memory module addresses are sequentially aligned along the same address

range. This applies to program flash, data flash, ROM and all other peripherals.

Within the UCD3138xA family architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware

startup routines for PMBus communication and non-volatile (FLASH) memory download. This boot ROM is

executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is present, the

ROM code branches to the main FLASH-program execution. If there is no valid program, the device waits for a

program download through the PMBus.

The UCD3138xA family also supports customization of the boot program by allowing an alternative boot routine

to be executed from program FLASH. This feature enables assignment of a unique address to each device;

therefore, enabling firmware reprogramming even when several devices are connected on the same

communication bus.

There are three separate flash memory areas present inside the device. There are 4-32 kB program flash blocks

and 1-2 kB data flash area. The 32 kB program areas are organized as 8 k x 32 bit memory blocks and are

intended to be for the firmware programs. The blocks are configured with page erase capability for erasing blocks

as small as 1 kB per page, or with a mass erase for erasing the entire 32 kB array. The flash endurance is

specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data flash array is

organized as a 512 x 32 bit memory (32 byte page size). The data flash is intended for firmware data value

storage and data logging. Thus, the Data flash is specified as a high endurance memory of 20 k cycles with

embedded error correction code (ECC).

UCD3138128APFC Datasheet(PDF) 20 Page - Texas Instruments

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