TMS320DM814X datasheet(208/376 Pages) TI1

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x2M

Multiplier

REFCLK

DCOCLK

CLKOUT

DEV Clock

(

N +

( 2 1)

N +

DEV/AUX

Clock

Multiplier

REFCLK

CLKDCO

CLKOUT

(

N +

( 2 1)

N +

CLKOUTx

(Divide-by-1)

TMS320DM8148, TMS320DM8147

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

www.ti.com

Table 7-19. Switching Characteristics Over Recommended Operating Conditions for CLKOUTx (CLKOUT0

and CLKOUT1)(1) (2)

(see Figure 7-16)

OPP100

NO.

PARAMETER

UNIT

MIN

MAX

tc(CLKOUTx)

Cycle time, CLKOUTx

tw(CLKOUTxH)

Pulse duration, CLKOUTx high

0.45P

0.55P

tw(CLKOUTxL)

Pulse duration, CLKOUTx low

0.45P

0.55P

tt(CLKOUTx)

Transition time, CLKOUTx

0.05P

(1)

The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

(2)

P = 1/CLKOUTx clock frequency in nanoseconds (ns). For example, when CLKOUTx frequency is 200 MHz, use P = 5 ns.

Figure 7-16. CLKOUTx Timing

7.4.8

PLLs

The device contains 12 top-level PLLs, and 4 embedded PLLs (within the ARM Cortex-A8, PCIE, SATA,

and CSI) that provide clocks to different parts of the system. Figure 7-17 and Figure 7-18 show simplified

block diagrams of the Top-Level PLL and PLL_ARM. In addition, see the System Clocking Overview

(Figure 7-6) for a high-level view of the device clock architecture including the PLL reference clock

sources and connections.

Figure 7-17. Top-Level PLL Simplified Block Diagram

Figure 7-18. PLL_ARM Simplified Block Diagram

The reference clock for most of the PLLs comes from the DEV input clock, with select PLLs also having

the option to use the AUX input clock as a reference. Also, each PLL supports a Bypass mode in which

the reference clock can be directly passed to the PLL CLKOUT through a divider. All device PLL’s will

come-up in Bypass mode after reset.

For details on programming the device PLLs, see the Control Module chapter of the TMS320DM814x

DaVinci Digital Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

208

Power, Reset, Clocking, and Interrupts

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