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TMS320DM814x Datasheet(PDF) 211 Page - Texas Instruments |
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TMS320DM814x Datasheet(HTML) 211 Page - Texas Instruments |
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211 / 376 page ![]() TMS320DM8148, TMS320DM8147 www.ti.com SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 7.4.9 SYSCLKs In some cases, the system clock inputs and PLL outputs are sent to the PRCM Module for division and multiplexing before being routed to the various device Modules. These clock outputs from the PRCM Module are called SYSCLKs. Table Table 7-26 lists the device SYSCLKs along with their maximum supported clock frequencies. In addition, limits shown in these tables may be further restricted by the clock frequency limitations of the device modules using these clocks. For more details on Module Clock frequency limits, see Section 7.4.10 Module Clocks. Table 7-26. Maximum SYSCLK Clock Frequencies(1) MAX CLOCK FREQUENCY SYSCLK OPP100 (MHz) SYSCLK1 RSV SYSCLK2 RSV SYSCLK3 266 SYSCLK4 200 SYSCLK5 RSV SYSCLK6 100 SYSCLK7 RSV SYSCLK8 192 SYSCLK9 RSV SYSCLK10 48 SYSCLK11 RSV SYSCLK12 RSV SYSCLK13 RSV SYSCLK14 27 SYSCLK15 RSV SYSCLK16 27 SYSCLK17 RSV SYSCLK18 0.032768 SYSCLK19 192 SYSCLK20 192 SYSCLK21 192 SYSCLK22 RSV SYSCLK23 200 (1) The maximum frequencies listed in this table are valid for OPP100. Some of these frequencies have higher maximum values when OPP120 or OPP166 is used, see Table 7-4 Copyright © 2011–2013, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 211 Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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