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TMS320DM814x Datasheet(PDF) 234 Page - Texas Instruments |
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TMS320DM814x Datasheet(HTML) 234 Page - Texas Instruments |
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234 / 376 page  5 6 8 7 TCK RTCK 3 TCK TDO TDI/TMS 2 4 1 1a 1b TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com Figure 8-6. JTAG Timing Table 8-11. Timing Requirements for IEEE 1149.1 JTAG With RTCK (see Figure 8-6) OPP100/120/166 NO. UNIT MIN MAX 1 tc(TCK) Cycle time, TCK 51.15 ns 1a tw(TCKH) Pulse duration, TCK high (40% of tc) 20.46 ns 1b tw(TCKL) Pulse duration, TCK low (40% of tc) 20.46 ns 3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high (20% of (tc * 0.5)) 5.115 ns 3 tsu(TMS-TCK) Input setup time, TMS valid to TCK high (20% of (tc * 0.5)) 5.115 ns th(TCK-TDI) Input hold time, TDI valid from TCK high 10 ns 4 th(TCK-TMS) Input hold time, TMS valid from TCK high 10 ns Table 8-12. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK (see Figure 8-7) OPP100/120/166 NO. PARAMETER UNIT MIN MAX Delay time, TCK to RTCK with no selected subpaths (that is, 5 td(TCK-RTCK) ICEPick is the only tap selected - when the ARM is in the scan 0 21 ns chain, the delay time is a function of the ARM functional clock.) 6 tc(RTCK) Cycle time, RTCK 51.15 ns 7 tw(RTCKH) Pulse duration, RTCK high (40% of tc) 20.46 ns 8 tw(RTCKL) Pulse duration, RTCK low (40% of tc) 20.46 ns Figure 8-7. JTAG With RTCK Timing 234 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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