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TMS320DM814x Datasheet(PDF) 314 Page - Texas Instruments |
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TMS320DM814x Datasheet(HTML) 314 Page - Texas Instruments |
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314 / 376 page ![]() A1 A2 Processor Differential Clock Output Buffer DDR Differential CK Input Buffers Routed as Differential Pair A3 AT Rcp Clock Parallel Terminator A1 A2 A3 AT Rcp Cac DDR_1V5 0.1 µF + – + – + – = Rtt A2 A3 A4 AT Vtt A3 TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com Figure 8-63. ADDR_CTRL Routing for Four Mirrored DDR3 Devices 8.13.4.2.4.11.4 Two DDR3 Devices Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one bank (CS), 16-bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32-bits wide. These two devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB. 8.13.4.2.4.11.5 CK and ADDR_CTRL Topologies, Two DDR3 Devices Figure 8-64 shows the topology of the CK net classes and Figure 8-65 shows the topology for the corresponding ADDR_CTRL net classes. Figure 8-64. CK Topology for Two DDR3 Devices 314 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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