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TMS320DM814x Datasheet(PDF) 315 Page - Texas Instruments |
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TMS320DM814x Datasheet(HTML) 315 Page - Texas Instruments |
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315 / 376 page ![]() = Rcp Rcp Cac DDR_1V5 0.1 µF A2 A3 AT A2 A3 AT A1 A2 Processor Address and Control Output Buffer DDR Address and Control Input Buffers A3 AT Vtt Address and Control Terminator Rtt TMS320DM8148, TMS320DM8147 www.ti.com SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 Figure 8-65. ADDR_CTRL Topology for Two DDR3 Devices 8.13.4.2.4.11.6 CK and ADDR_CTRL Routing, Two DDR3 Devices Figure 8-66 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-67 shows the corresponding ADDR_CTRL routing. Figure 8-66. CK Routing for Two Single-Side DDR3 Devices Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 315 Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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