TMS320DM814X datasheet(322/376 Pages) TI1

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TMS320DM8148, TMS320DM8147

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

www.ti.com

Table 8-75. CK and ADDR_CTRL Routing Specification(1)(2)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

A1+A2 length

2500

mils

A1+A2 skew

mils

A3 length

660

mils

A3 skew(3)

mils

A3 skew(4)

125

mils

A4 length

660

mils

A4 skew

mils

AS length

100

mils

AS skew

100

mils

AS+/AS- length

mils

AS+/AS- skew

mils

AT length(5)

500

mils

AT skew(6)

100

mils

AT skew(7)

mils

CK/ADDR_CTRL nominal trace length(8)

CACLM-50

CACLM

CACLM+50

mils

Center-to-center CK to other DDR3 trace spacing(9)

Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)

Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(9)

CK center-to-center spacing(11)

(12)

CK spacing to other net(9)

Rcp(13)

Zo-1

Zo+

Rtt(13)(14)

Zo-5

Zo+5

(1)

The use of vias should be minimized.

(2)

Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump

between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.

(3)

Non-mirrored configuration (all DDR3 memories on same side of PCB).

(4)

Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).

(5)

While this length can be increased for convenience, its length should be minimized.

(6)

ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.

(7)

CK net class only.

(8)

CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see

Section 8.13.4.2.4.13.1, Figure 8-78, and Figure 8-79.

(9)

Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.

(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.

(11) CK spacing set to ensure proper differential impedance.

(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,

center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-

ended impedance, Zo.

(13) Source termination (series resistor at driver) is specifically not allowed.

(14) Termination values should be uniform across the net class.

8.13.4.2.4.13.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew

must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces

up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,

a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as

DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four

DQLMs, DQLM0–DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0–DQLM1.

NOTE

It is not required, nor is it recommended, to match the lengths across all bytes. Length

matching is only required within each byte.

322

Peripheral Information and Timings

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