TMS320DM814X datasheet(323/376 Pages) TI1

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DQLMX3

DQLMY0

DQLMY3

DQLMY2

DB3

DQLMX2

DB2

DQ[23:31]/DM3/DQS3

DQ[16:23]/DM2/DQS2

DQLMX1

DB1

DB0

DQLMX0

DQ[8:15]/DM1/DQS1

DQ[0:7]/DM0/DQS0

DQLMY1

DB0 - DB3 represent data bytes 0 - 3.

TMS320DM8148, TMS320DM8147

www.ti.com

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum

possible Manhattan distance can be determined given the placement. Figure 8-80 shows this distance for

four loads. It is from this distance that the specifications on the lengths of the transmission lines for the

data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-76.

There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the

byte; therefore:

DQLM0 = DQLMX0 + DQLMY0

DQLM1 = DQLMX1 + DQLMY1

DQLM2 = DQLMX2 + DQLMY2

DQLM3 = DQLMX3 + DQLMY3

Figure 8-80. DQLM for Any Number of Allowed DDR3 Devices

Table 8-76. Data Routing Specification(1)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

DB0 nominal length(2)(3)

DQLM0

mils

DB1 nominal length(2)(4)

DQLM1

mils

DB2 nominal length(2)(5)

DQLM2

mils

DB3 nominal length(2)(6)

DQLM3

mils

DBn skew(7)

mils

DQSn+ to DQSn- skew

mils

DQSn to DBn skew(7)(8)

mils

Center-to-center DBn to other DDR3 trace spacing(9)(10)

Center-to-center DBn to other DBn trace spacing (9)(11)

DQSn center-to-center spacing(12)

(13)

DQSn center-to-center spacing to other net(9)

(1)

External termination disallowed. Data termination should use built-in ODT functionality.

(2)

DQLMn is the longest Manhattan distance of a byte. For definition, see Section 8.13.4.2.4.13.2 and Figure 8-80.

(3)

DQLM0 is the longest Manhattan length for the net classes of Byte 0.

(4)

DQLM1 is the longest Manhattan length for the net classes of Byte 1.

(5)

DQLM2 is the longest Manhattan length for the net classes of Byte 2.

(6)

DQLM3 is the longest Manhattan length for the net classes of Byte 3.

(7)

Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.

(8)

Each DQS pair is length matched to its associated byte.

(9)

Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.

(10) Other DDR3 trace spacing means other DDR3 net classes not within the byte.

(11) This applies to spacing within the net classes of a byte.

(12) DQS pair spacing is set to ensure proper differential impedance.

(13) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,

center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-

ended impedance, Zo.

Peripheral Information and Timings

323

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