PC87591L datasheet(27/437 Pages) NSC

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1.0 Introduction (Continued)

Revision 1.07

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The PC87591x hardware arbitrates flash usage by the core firmware and the host processor BIOS program when Shared-

BIOS configuration is selected. Flash sharing is based on in-parallel “cycle stealing” so both the host processor and the core

can execute code in parallel from the same memory device. The host processor typically copies the flash contents to the

host’s main memory (DRAM) on system boot to improve access time to it and enable execution when the flash’s contents

is compressed. It is important to do this early in the boot process to reduce resource contention between the core and the

host.

The PC87591E and PC87591S flash memory may be updated by the core firmware, host software, JTAG protocol or via the

parallel interface. Protection mechanisms limit the read, write and erase rights of various sources to guarantee flash content

integrity and confidentiality, where applicable. See Section 4.16.6 on page 226 for more details about the flash update and

protection mechanisms.

In DEV environment, access to the main block of the flash is disabled and replaced by off-chip SRAM to enable easy and

efficient debugging. For operation in OBD environment, the application should be linked with the TMON program and loaded

into the on-chip flash. See the CompactRISC

 PC87591x Tmonlib Version 3.1.2.3 Release Letter, March 2001, for infor-

mation on TMON program integration and specification of requirements.

The PC87591L is equipped with a small pre-programed flash, which functions as a boot ROM. The devices are shipped pre-

programed and may not be programed in the field. Some devices intended for development purpose may be programed via

the JTAG interface.

The information block of the flash has two dedicated areas: one for factory parameters and another for the protection word.

The factory parameters are saved during the device production and are used for various calibrations (see Appendix B.1 on

page 434 for the factory parameters block organization and usage). The protection word holds information on access rights

to the flash and the size of the core and host boot blocks. See Section 4.16.6 on page 226 and Appendix B.2 on page 435

for more information.

1.3.4

Peripherals

The ICU (Interrupt Control Unit) collects interrupts from various internal and external (through the MIWU) sources and no-

tifies the core of the event using the vectored interrupt mechanism. It supports 31 maskable interrupt inputs (see Table 16

on page 99 for the interrupt assignment) and a non-maskable interrupt (NMI) through the PFAIL input.

The MIWU (Multi-Input Wake-Up) module enables collecting various internal and external interrupt sources (events), gen-

erates interrupts in Active mode and enables the PC87591x to return from Idle mode to Active mode. The core can individ-

ually enable or disable the various wake-up conditions. The PC87591x has a total of 28 wake-up signals, some of which are

grouped to generate a single interrupt signal to the ICU.

The PMC (Power Management Controller) controls PC87591x power consumption according to the required activity level.

Power consumption is adjusted by controlling the clock frequency and selective enabling/disabling of three power modes:

Active, Idle and Power Off. Activity can be resumed by external events (through the MIWU) or internal events, such as a

periodic wake-up.

The Clock Generator provides clocks for the various core-related on-chip modules. These clocks are generated directly

from a 32.768 KHz crystal or from the on-chip High-Frequency Clock Generator (HFCG). The HFCG generates the high-

frequency clock using the RTC’s 32.768 KHz clock signal as a reference. The PC87591x operation frequency is set by pro-

graming the HFCG registers. The PMC enables and disables high-frequency clock generation, according to the required

power mode.

The GPIO Ports (General-Purpose Input/Output) module consists of up to 117 GPIO signals (84 in the 128-pin package)

that provide interface and control for the PC system. Some of these I/O port signals share their pins with an alternate function

(see Table 8 on page 54) and may be mutually exclusive. When configured as inputs, some of these signals can interrupt

the core when an event is detected, even if the device is in Idle mode. An example is the SWIN input, which is dedicated to

the PC On/Off switch.

Internal keyboard scanning is supported by 16 open-drain output signals and eight input signals. Switch-based keyboard

matrices are supported with CMOS Schmitt trigger inputs with internal pull-up resistors. Resistive keyboard matrices are

supported with analog comparator inputs with variable thresholds and optional internal pull-up resistors. Section 4.14 on

page 208 describes the functionality of the analog comparator (ACM) circuitry. For power efficiency, the inputs include an

interrupt and a wake-up capability, so that pressing/releasing keys may be identified without scanning the keyboard matrix

in either Active or Idle modes. The keyboard interrupt is controlled by the MIWU.

The PS/2 Interface enables interface with industry-standard, PS/2-compatible keyboard, mouse and other pointing devic-

es. The PC87591x supports up to four PS/2 devices via its dedicated 4-channel PS/2 interface module. Each channel has

two quasi-bidirectional signals. The symmetric structure of the channels enables software-controlled interchanging of devic-

es to channels.

The PC87591x includes a hardware accelerator, which allows the PS/2 channels to be controlled with minimal software

overhead. It also eliminates the sensitivity to interrupt latency that characterized traditional solutions.

PC87591L Datasheet(PDF) 27 Page - National Semiconductor (TI)

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