PC87591L datasheet(36/437 Pages) NSC

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1.0 Introduction (Continued)

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Revision 1.07

Accessing Expansion Memory

Expansion Memory Configuration is available in PC87591x versions packed in 176-pin packages. Access to it is enabled

only after:

●

The pins used for the memory interface are conﬁgured to operate as Expansion Memory interface signals (see

Section 2.4 on page 54 for details on the alternate functions conﬁguration).

●

The BIU Zone 0 Conﬁguration register (SZCFG0), which controls the memory access parameters (e.g., bus width and

access time), is set to support the conﬁguration in use.

The interface signals to the Expansion Memory are:

●

8-bit ﬂash or SRAM: SEL0, RD, WR0, D0-7 and A0-19 (fewer address lines may be used with a smaller ﬂash).

●

16-bit ﬂash or SRAM: SEL0, RD, WR0-1, D0-15 and A1-19 (fewer address lines may be used with a smaller ﬂash).

Figure 8 shows the External Memory Address Range mapping to the core, in the PC87591E and PC87591S devices.

Figure 9 shows the External Memory Address Range mapping to the core in the PC87591L device. Note that in PC87591L

devices, the External Memory is aliased to low addresses of the core address space, enabling access to memory locations

in the flash from both an address in the low memory and an address in the upper part of the memory.

4 K

64 K

Off-Chip Base Memory

On-Chip Base Memory

Figure 7. Base Memory Address Mapping - PC87591L

4 K

Core Address Map

00 0000

00 0FFF

Zone 1

Access Time

Control

PC87591L

Flash Size

2 M

1 M

PC87591L Datasheet(PDF) 36 Page - National Semiconductor (TI)