PC87591L datasheet(8/437 Pages) NSC

8 / 437 page

Table of Contents (Continued)

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Revision 1.07

Control Signals .................................................................................................... 72

4.1.4

Early Write Bus Cycle .................................................................................................. 72

4.1.5

Late Write Bus Cycle ................................................................................................... 74

4.1.6

Normal Read Bus Cycle .............................................................................................. 76

4.1.7

Fast Read Bus Cycle ................................................................................................... 79

4.1.8

I/O Expansion Bus Cycles ........................................................................................... 80

4.1.9

Development Support .................................................................................................. 81

Bus Status Signals ............................................................................................... 81

Core Bus Monitoring ............................................................................................ 82

4.1.10

BIU Registers .............................................................................................................. 83

BIU Configuration Register (BCFG) ..................................................................... 83

I/O Zone Configuration Register (IOCFG) ........................................................... 84

Static Zone Configuration Register (SZCFGn) .................................................... 85

4.1.11

Usage Hints ................................................................................................................. 86

4.2

DMA CONTROLLER (DMAC) ................................................................................................... 87

4.2.1

Features ...................................................................................................................... 87

4.2.2

Functional Description ................................................................................................. 87

4.2.3

Channel Assignment in PC87591x .............................................................................. 87

4.2.4

Transfer Types ............................................................................................................ 88

Direct (Fly-By) Transfers ...................................................................................... 88

Indirect (Memory-to-Memory) Transfers .............................................................. 89

4.2.5

Bus Policy .................................................................................................................... 90

Intermittent Operation Mode ................................................................................ 90

Continuous Operation Mode ................................................................................ 90

4.2.6

Operation Modes ......................................................................................................... 91

Single Transfer Operation .................................................................................... 91

Double Buffer Operation ...................................................................................... 91

Auto-Initialize Operation ...................................................................................... 92

4.2.7

Software DMA Request ............................................................................................... 92

4.2.8

DMAC Registers .......................................................................................................... 92

DMAC Register Map ............................................................................................ 92

Device A Address Counter Register (ADCAn) ..................................................... 93

Device A Address Register (ADRAn) .................................................................. 93

Device B Address Counter Register (ADCBn) ..................................................... 93

Device B Address Register (ADRBn) .................................................................. 93

Block Length Counter Register (BLTCn) ............................................................. 94

Block Length Register (BLTRn) ........................................................................... 94

DMA Control Register (DMACNTLn) ................................................................... 94

DMA Status Register (DMASTATn) ..................................................................... 96

4.2.9

Usage Hints ................................................................................................................. 97

4.3

INTERRUPT CONTROL UNIT (ICU) ......................................................................................... 98

4.3.1

Features ...................................................................................................................... 98

4.3.2

Non-Maskable Interrupt (NMI) ..................................................................................... 98

External NMI Inputs ............................................................................................. 98

Non-Maskable Interrupt Processing .................................................................... 98

PFAIL Input .......................................................................................................... 98

4.3.3

Maskable Interrupts ..................................................................................................... 98

Maskable Interrupt Vectors .................................................................................. 99

PC87591L Datasheet(PDF) 8 Page - National Semiconductor (TI)

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