PC87591L datasheet(78/437 Pages) NSC

78 / 437 page

4.0 Embedded Controller Modules (Continued)

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Revision 1.07

Other SZCFGn

configuration

HOLD field in SZCFGn reg. = 0

HOLD field in SZCFGn reg.

≠ 0

WAIT field in SZCFGn reg.

≠ 0

WAIT field in SZCFGn reg. = 0

Address placed on A0-19;

SELn: activated.

RD: active

Address on A0-19 invalid/changed;

SELn and RD: inactive.

RD: active;

End of T2: Data is sampled.

Internal waits corresponding to WAIT field in SZCFGn register.

TIW

TBW

begin

Hold cycles completed

Thold

T2B

end

{BW = 1 or BRE = 0

or core attempts to read a byte}

BW = 0; {WBR,BRE} = 11;

Core attempts to read a word

Next address on A0-19;

End of T2B: Data sampled.

Hold cycles according

to HOLD field in SZCFGn reg.

First Thold: SELn

and RD are deactivated

In SZCFGn reg.: {BW,WBR,BRE} = 001

Core attempts to read a word

Figure 20. Normal Read Bus Cycle

Note: References to SZCFGn also apply to the IOCFG register.

References to SELn also apply to the SELIO signal.

TBW and T2B states do not exist in bus cycles of the IO zone.

Internal waits completed

In SZCFGn reg.: HOLD

≠ 0

Next address

on A0-19

In SZCFGn reg.:

PC87591L Datasheet(PDF) 78 Page - National Semiconductor (TI)

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