PC87591L datasheet(75/437 Pages) NSC

75 / 437 page

4.0 Embedded Controller Modules (Continued)

Revision 1.07

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At the first TIW or T2 (when there are no TIW cycles), the data is placed on the data bus. The bus cycle is completed at T2;

at this point, WR0-1 are deactivated. The address and data remain valid until T2 is completed.

After T2, the number of Thold cycles specified by HOLD in SZCFGn register (may be 0) is added to the transaction. When

Thold cycles are added, the address and data remain valid until the end of the last Thold cycle. SELn (or SELIO) is deactivated

on the first Thold cycle. When no Thold cycles are specified, SELn (or SELIO) is deactivated in the clock cycle after T2 unless

another read or write from the same zone follows. The data is put in TRI-STATE in the clock cycle after the last Thold or T2

(if no Thold cycle is configured); see Figures 15, 16 and 17.

Hold cycles

according to

HOLD in

SZCFGn reg.

HOLD field in SZCFGn reg.

≠ 0

WAIT field in SZCFGn reg.

≠ 0

WAIT field in SZCFGn reg. = 0

First Thold;

SELn: inactive.

Hold cycles completed

Address placed on A0-19;

SELn: activated;

WR0-1: activated.

Data placed

on D0-15

Internal waits completed

HOLD field in SZCFGn reg. = 0

Address on A0-19 invalid/changed;

Data put in TRI-STATE;

SELn: inactive.

Data placed on D0-15;

WR0-1: inactive.

Internal waits corresponding to WAIT field in SZCFGn register

Thold

end

begin

Note: References to SZCFGn also apply to the IOCFG register.

References to SELn also apply to the SELIO signal.

TIW

Figure 15. Late Write Bus Cycle

PC87591L Datasheet(PDF) 75 Page - National Semiconductor (TI)

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