AS4SD32M16DG-75SLASHXT datasheet(2/52 Pages) MICROSS

2 / 52 page

SDRAM

AS4SD32M16

Rev. 2.0 10/13

Micross Components reserves the right to change products or speciﬁcations without notice.

GENERAL DESCRIPTION

The 512Mb SDRAM is a high-speed CMOS, dynamic

random-access memory containing 536, 870, 912 bits. It is

internally conﬁgured as a quad-bank DRAM with a synchro-

nous interface (all signals are registered on the positive edge

of the clock signal, CLK). Each of the 67,108,864-bit banks

is organized as 8,192 rows by 1024 columns by 16 bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue for a

programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command,

which is then followed by a READ or WRITE command. The

address bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed (BA0, BA1

select the bank; A0-A12 select the row). The address bits regis-

tered coincident with the READ or WRITE command are used

to select the starting column location for the burst access.

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page,

with a burst terminate option. An auto precharge function may

be enabled to provide a self-timed row precharge that is initiated

at the end of the burst sequence.

The 512Mb SDRAM uses an internal pipelined architecture

to achieve high-speed operation. This architecture is compatible

with the 2n rule of prefetch architectures, but it also allows the

column address to be changed on every clock cycle to achieve

a high-speed, fully random operation. Precharging one bank

while accessing one of the other three banks will hide the pre-

charge cycles and provide seamless, high-speed, random-access

operation.

The 512Mb SDRAM is designed to operate in 3.3V

memory systems. An auto refresh mode is provided, along with

a power-saving, power-down mode. All inputs and outputs are

LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating

performance, including the ability to synchronously burst data at

a high data rate with automatic column-address generation, the

ability to interleave between internal banks to hide precharge

time and the capability to randomly change column addresses

on each clock cycle during a burst access.

FUNCTIONAL BLOCK DIAGRAM

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

A0–A12,

BA0, BA1

DQML,

DQMH

ADDRESS

1024

(x16)

16384

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 1,024 x 16)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ15

DATA

INPUT

DATA

OUTPUT

BANK1

BANK2

BANK3

REFRESH

COUNTER

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