AS4SD32M16DG-75SLASHXT datasheet(21/52 Pages) MICROSS

21 / 52 page

SDRAM

AS4SD32M16

Rev. 2.0 10/13

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WRITE with Auto Precharge

3. Interrupted by a READ (with or without auto precharge);

A READ to bank m will interrupt a WRITE on bank n when

registered, with the data-out appearing CAS latency later. The

PRECHARGE to bank n will begin after t

WR is met, where tWR

begins when the READ to bank m is registered. The last valid

WRITE to bank n will be data-in registered one clock prior to

the READ to bank m (Figure 26).

4. Interrupted by a WRITE (with or without auto precharge):

A WRITE to bank m will interrupt a WRITE on bank n when

registered. The PRECHARGE to bank n will begin after t

WR is

met, where t

WR begins when the WRITE to bank m is registered.

The last valid data WRITE to bank n will be data registered one

clock prior to the WRITE to bank m (Figure 26).

FIGURE 26: WRITE With Auto Precharge Interrupted by a READ

FIGURE 27: WRITE With Auto Precharge Interrupted by a WRITE

AS4SD32M16DG-75/XT Datasheet(PDF) 21 Page - Micross Components