THS8083APZP datasheet(48/64 Pages) TI

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5–4

5.4.4

I2C Interface

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIL

Low-level input voltage

0.99

VIH

High-level input voltage

2.31

f(SCL)

SCL clock frequency

400†/100‡

kHz

t(LOW)

Low period of SCL

Valid for I2C fast mode support only.

1.3

µs

t(HIGH)

High period of SCL

Valid for I2C fast mode su

ort only.

See footnotes to SCL clock frequency.

0.6

µs

th(DATA)

Data hold time

0§

µs

tsu(DATA)

Data setup time

100¶

µs

C(b)

Capacitive load for each bus line#

400

† For DTO clock frequencies 25 MHz minimum (I2C fast mode)

‡ For DTO clock frequencies below 25 MHz (I2C normal mode)

§ The device must internally provide a hold time of 300 ns for the SDA signal (referred to VIH(min) of the SCL signal) in order to bridge the undefined

region of the falling edge of SCL.

¶ If the device is used in a standard mode I2C system, the requirement of tsu(DATA)>=250 ns must be met.

# Cb= total capacitance of one bus line in pF

5.4.5

ADC Channel

5.4.5.1 DC Accuracy†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Integral nonlinearity (INL)

PLL (see Note 7)

±1

LSB

Integral nonlinearity (INL)

PLL (see Note 7)

–2

±1

LSB

Differential nonlinearity (DNL)

PLL (see Note 8)

LSB

Differential nonlinearity (DNL)

PLL (see Note 8)

–1

1.5

LSB

No missing codes

Assured

Gain error

ADC_INTREF (see Note 9)

Offset error

ADC_INTREF (see Note 10)

† Assured at nominal voltage supply levels only.

NOTES:

7. Integral nonlinearity (INL) —Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full

scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond

the last code transition. The deviation is measured from the center of each particular code to the true straight line between these

two end points.

8. Differential nonlinearity (DNL)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this

ideal value. Therefore, this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here

as the step size for the device under test (i.e., last transition level – first transition level)/(2n – 2). Using this definition for DNL

separates the effects of gain and offset error. A DNL of less than

±1 LSB ensures no missing codes. A DNL of less than ±1/2 LSB

assures monotonic behavior.

9. Gain error—The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale (the voltage applied

to the REFBI terminal). The last transition should occur for an analog value 1/2 LSB below nominal positive full scale (the voltage

applied to the REFTI terminal). Gain error is defined here as the deviation from the ideal location of the highest transition level on

the ADC transfer function.

10. Offset error—The first code transition should occur at a level 1/2 LSB above zero. Offset is defined as the deviation of the actual

first code transition from that point.

THS8083APZP Datasheet(PDF) 48 Page - Texas Instruments

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