THS8083APZP datasheet(51/64 Pages) TI

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5–7

5.4.9.2 Closed Loop

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f(HS)

HS locking range

100

kHz

t(acq)

Lock-in time

See Note 16

t(JCS)

Short-term jitter

See Note 16

925 (p–p)

245 (rms)

1400 (p–p)

450 (rms)

t(JCL)

Long-term jitter

See Note 16

1000 (p–p)

250 (rms)

1500 (p–p)

485 (rms)

NOTE 16: PLL characterization:

•

Short term jitter in open loop or closed loop is defined as the variation within one PLL update period (within the same video line) of

the clock rising edge. This is measured visually by capturing the clock and displaying it on a digital scope with a persistency of one

video line. Numerically, the time instants of the rising edges, at a defined voltage level, of a number of clock cycles (N = 800) are

captured at a high sampling rate. The average clock time period is calculated from these time instants. The deviation between

each actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value

along one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.

•

Long term jitter in closed loop is defined as the variation over one video frame of the Nth clock rising edge on each line. This is

measured by capturing the time instant at a defined level on the rising edge of the Nth clock after HS is reached on each line. The

calculation uses the same principle used with short term jitter, but now takes one sample on every line and N = 800 lines.

5.4.10 Typical Plots (25

°C and Measured for Standard VESA Graphics Formats)

NOTE: The THS8083 is configured for each video mode with I2C register settings as specified

in application note Using THS8083 for PC Graphics and Component Video Digitizing.

Figure 5–2. Power Consumption

f – Frequency – MHz

1000

1100

1200

1300

1400

1500

1600

102030405060708090

100

VCC = 3.3 V

POWER

FREQUENCY

f – Frequency – MHz

100

150

200

250

300

350

102030405060708090

100

Total Analog

CURRENT

FREQUENCY

DVDD

Total Digital

AVDD_REF

AVDD_PLL

AVDD_CH1+AVDD_CH2_3

DVDD_PLL

THS8083APZP Datasheet(PDF) 51 Page - Texas Instruments

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