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THS8083APZP Datasheet(PDF) 57 Page - Texas Instruments |
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THS8083APZP Datasheet(HTML) 57 Page - Texas Instruments |
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57 / 64 page ![]() A–1 Appendix A PLL Formulas and Register Settings If: F(XTL) = frequency of external crystal or master clock connected to XTL1 input of THS8083A F(VCO) = frequency of THS8083A–internal VCO F(DTO) = frequency of THS8083A–internal DTO F(DTOCLK) = frequency of externally available DTO clock output F(HS) = frequency of HS input CLKDIV = clock output divider setting VCODIV = feedback divider in THS8083A–internal analog PLL loop TERMCNT = feedback divider in THS8083A–internal digital PLL loop DTO_INC = DTO increment (when NOM_INC is programmed, DTO_INC is initialized to NOM_INC) Then: F(VCO) = F(XTL) x VCODIV F(DTO) = 32 x F(VCO) / DTO_INC F(DTOCLK) = F(DTO) / CLKDIV And, if PLL is locked: F(DTOCLK) = TERMCNT * F(HS) Summarizing: DTO_INC = [32xF(XTL)xVCODIV] / [F(DTOCLK)xCLKDIV] The formats of DTO_INC and NOM_INC: Both are 33-bit values consisting of a 6-bit integer and a 27-bit fractional part. So, in hexadecimal notation, the value is between 00.0000000hex and 3F.7FFFFFFhex. The decimal value of the increment is: <integer part>.<fractional part interpreted as integer value>x2^(–27). This means, to arrive at the decimal value of the increment: 1. Interpret the 6 MSBs as an integer value 2. Interpret the 27 LSBs expressed as a decimal integer value and multiply this by 2^(–27) to arrive at a fractional value 3. Add 1 and 2. Additional restrictions: – NOM_INC should be within the range [16,32]. – CLKDIV should be chosen for different output clock frequency ranges as shown in register map description for SEL_CLK. Examples: 1. For generating the XGA@75Hz pixel clock of 78.75 MHz, with F(XTL) = 14.381818 MHz and VCODIV=8: NOM_INC = [32x14.31818x8]/[78.75x2] = 23.272724... Since 23d = 17h and INT(0.272724 … x 2^27) = 36604438d = 22E8A16 hex, this can be written as 0x17.22E8A16 or as a contiguous 33 bit number: 010111010001011101000101000010110 = 0BA2E8A16 hex, i.e., the default setting for NOM_INC (see register map). |
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