FT4222HQ-C-R datasheet(11/49 Pages) FTDI

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FT4222H USB2.0 TO QUADSPI/I2C BRIDGE IC

1.3

Document No.: FT_001011 Clearance No.: FTDI#405

4.2

Functional Block Descriptions

The following paragraphs detail each function within the FT4222H. Please refer to the block diagram

shown in Figure 2.1

USB2.0 UTMI PHY. The Universal Transceiver Macrocell Interface (UTMI) is a physical interface cell.

This block handles the full speed and high speed SERDES (serialise - deserialise) function for the USB

TX/RX data. It also provides the clocks for the rest of the chip. A 12 MHz crystal should be connected to

the XSCI and XSCO pins. A 12k Ohm resistor should be connected between REF and GND on the PCB.

The UTMI PHY functions include:



Supports 480 Mbit/s "Hi-Speed" (HS) and 12 Mbit/s “Full Speed” (FS).



SYNC/EOP generation and checking.



Data and clock recovery from a serial stream on the USB.



Bit-stuffing/unstuffing; bit stuff error detection.



Manages USB Resume, Wake Up and Suspend functions.

Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks

USB Device Controller. The USB Device controller in the FT4222H controls and manages the interface

between the UTMI PHY and the interfaces of the chip. It provides 9 endpoints to fit into the FT4222H

applications.

The USB Device Controller function includes:



Endpoint-0 for a control pipe with max packet size 64 Bytes



4 endpoints for bulk-in pipe with configurable max packet size up to 512 Bytes



4 endpoints for bulk-out pipe with configurable max packet size up to 512 Bytes



Multiple interfaces configuration support



Suspend detection and power management



Remote wake-up support



Fully compatible to USB2.0 specification requirement

Endpoint Buffer. For fulfilling the max packet size requirement and high performance data transfer

throughput, the Endpoint Buffer is 4160 bytes SRAM with configurable size management to each endpoint.

It can be configured as single or double buffers and adjustable size for each endpoint.

QuadSPI Master/Slave Controller. The QuadSPI is a fully configurable SPI master/slave device, which

allows the user to configure polarity and phase of the serial clock signal SCK. When SPI is configured as a

master, it can be configured automatically to drive slave select outputs (SS3O – SS0O), and address the

SPI slave device to exchange serially shifted data. The data bus can be configured as single (1bit), dual

(2-bits) and quad (4-bits) mode for different transfer requests and applications. The interface operating

clock can be easily configured up to 30MHz. When SPI is configured as a slave, the SPI engine can

support one slave port and operate a single data mode transfer. The max acceptable operating clock can

be up to 20MHz. The QuadSPI controller can be configured via a support library, LibFT4222. For details

refer to the User Guide For LibFT4222.

QuadSPI as master functions include:



Single Mode (1-bit) data transfer with full duplex serial data transfer



Dual Mode (2-bit) data transfer



Quad Mode (4-bit) data transfer



Up to 4 SPI slave channels can be addressed via pins SS3O~SS0O



Shared data bus to minimize related pin counts



4 types of transfer format can be selected by Phase and Polarity



Configurable interface clock on SCK as 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of 80MHz,

60MHz,48MHz and 24MHz

FT4222HQ-C-R Datasheet(PDF) 11 Page - Future Technology Devices International Ltd.

FT4222HQ-C-R Datasheet(HTML) 11 Page - Future Technology Devices International Ltd.

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