FT4222HQ-C-R datasheet(19/49 Pages) FTDI

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FT4222H USB2.0 TO QUADSPI/I2C BRIDGE IC

1.3

Document No.: FT_001011 Clearance No.: FTDI#405

Table5.3 shows the timing information for QuadSPI with VCCIO equal to 1.8V and with 5pF loading on all

the related pins. The required setup time for input path is increasing since VCCIO=1.8V. The maximum

operating frequency of SCK is recommended not exceeded 30MHz.

Parameter

Min (ns)

Typ(ns)

Max(ns)

Description

T1@master

T2+T3

SCK Period when QuadSPI as master

T1@slave

Acceptable SCK Period when QuadSPI as slave device

16.67

SCK HIGH, related to the operating clock and ratio

16.67

SCLK LOW, related to the operating clock and ratio

T3-2.1

T3-1.2

Data output path: setup time to corresponding SCK edge

T2+0.1

T2+0.6

Data output path: hold time to corresponding SCK edge

8.6

16.5

Data input path: required setup time to corresponding

SCK edge

0.1

Data input path: required hold time to corresponding SCK

edge

6*T1

SSxO setup time to 1st SCK period boundary

6*T1

SSxO hold time from last SCK period boundary

T10@master

6*T1

Idle time on SCK between byte boundary when master

T10@slave

Idle time on SCK between byte boundary when slave

Table 5.3 SPI Timing for VCCIO=1.8V with 5pF output pin load

FT4222HQ-C-R Datasheet(PDF) 19 Page - Future Technology Devices International Ltd.

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