STM32F102xx datasheet(25/41 Pages) STMICROELECTRONICS

25 / 41 page

DocID14574 Rev 13

25/41

STM32F10xx8 STM32F10xxB

STM32F10xx8 and STM32F10xxB silicon limitations

Workaround

If the master device allows it, use the clock stretching mechanism by programming the bit

NOSTRETCH=0 in the I2C_CR1 register.

If the master device does not allow it, ensure that the software writes to the data register fast

enough after TXE or ADDR events. For instance, use an interrupt on the TXE or ADDR flag

and boost its priority to the higher level, or use DMA. Use this "NOSTRETCH" mode with a

slow I2C bus speed.

Note:

The first data byte to transmit must be written in the data register after the ADDR flag is

cleared, and before the next SCL rising edge, so that the time window for writing the first

data byte in the data register is less than tLOW.

If this is not possible, a workaround can be used:

Clear the ADDR flag

Wait for the OVR flag to be set

Clear OVR and write the first data byte.

Then the time window for writing the next data byte will be the time to transfer one byte. In

this case, the master must discard the first received data byte.

STM32F102xx Datasheet(PDF) 25 Page - STMicroelectronics