AS4C64M8D2 datasheet(17/59 Pages) ALSC

17 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

 Burst read with auto precharge

If A10 is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2

SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read

with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-

Precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start

point of Auto-precharge operation will be delayed until tRTP(min) is satisfied.

In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens

(not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-

Precharge to the next Activate command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-

Precharge to the next Activate command is AL + 2 + tRTP + tRP. Note that both parameters tRTP and tRP have to be

rounded up to the next integer value. In any event internal precharge does not start earlier than two clocks after

the last 4-bit prefetch.

A new bank active (command) may be issued to the same bank if the following two conditions are satisfied

simultaneously:

(1) The RAS# precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins.

(2) The RAS# cycle time (tRC) from the previous bank activation has been satisfied.

 Burst write with auto precharge

If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2

SDRAM automatically begins precharge operation after the completion of the burst write plus Write recovery time

(tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the

following two conditions are satisfied.

(1) The data-in to bank activate delay time (WR + tRP) has been satisfied.

(2) The RAS# cycle time (tRC) from the previous bank activation has been satisfied.

Table 12. Precharge & Auto Precharge Clarification

From Command

To Command

Minimum Delay between “From

Command” to “To Command”

Unit Note

Read

Precharge (to same Bank as Read)

AL+BL/2+max(RTP,2)-2

tCK 1,2

Precharge All

AL+BL/2+max(RTP,2)-2

Read w/AP

Precharge (to same Bank as Read w/AP)

AL+BL/2+max(RTP,2)-2

tCK 1,2

Precharge All

AL+BL/2+max(RTP,2)-2

Write

Precharge (to same Bank as Write)

WL+BL/2+tWR

tCK

Precharge All

WL+BL/2+tWR

Write w/AP

Precharge (to same Bank as Write w/AP)

WL+BL/2+tWR

tCK

Precharge All

WL+BL/2+tWR

Precharge

Precharge (to same Bank as Precharge)

tCK

Precharge All

Precharge

tCK

Precharge All

NOTE 1: RTP [cycles] =RU {tRTP [ns]/tCK (avg) [ns]}, where RU stands for round up.

NOTE 2: For a given bank, the precharge period should be counted from the latest precharge command, either

one bank precharge or precharge all, issued to that bank.The precharge period is satisfied after tRP or tRPall(=tRP

for 4 bank device) depending on the latest precharge command issued to that bank.

AS4C64M8D2 Datasheet(PDF) 17 Page - Alliance Semiconductor Corporation

AS4C64M8D2 Datasheet(HTML) 17 Page - Alliance Semiconductor Corporation

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