AS4C64M8D2 datasheet(1/59 Pages) ALSC

Part #	AS4C64M8D2

Description	Fully synchronous operation

PDF	59 Pages

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Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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AS4C64M8D2

Confidential

1

Rev. 1.0

Feb. /2014

512M – (64M x 8 bit) DDRII Synchronous DRAM (SDRAM)

Confidential

(Rev. 1.0, Feb. /2014)

Features

 JEDEC Standard Compliant

 JEDEC standard 1.8V I/O (SSTL_18-compatible)

 Power supplies: VDD & VDDQ = +1.8V  0.1V

 Operating temperature: 0 – 95 °C

 Supports JEDEC clock jitter specification

 Fully synchronous operation

 Fast clock rate: 400 MHz

 Differential Clock, CK & CK#

 Bidirectional single/differential data strobe

 4 internal banks for concurrent operation

 4-bit prefetch architecture

 Internal pipeline architecture

 Precharge & active power down

 Programmable Mode & Extended Mode registers

 Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5

 WRITE latency = READ latency - 1 tCK

 Burst lengths: 4 or 8

 Burst type: Sequential / Interleave

 DLL enable/disable

 On-die termination (ODT)

 RoHS compliant

 Auto Refresh and Self Refresh

 8192 refresh cycles / 64ms

-Average refresh period

7.8

s @ 0℃ ≦TC≦ +85℃

3.9

s @ +85℃ ＜TC≦ +95℃

 60-ball 8 x 10 x 1.2mm (max) FBGA package

- All parts are ROHS Compliant

Overview

The 512Mb DDR2 SDRAM is a high-speed CMOS

Double-Data-Rate-Two (DDR2), synchronous dynamic

random - access memory (SDRAM) containing 512

Mbits in an 8-bit wide data I/Os. It is internally

configured as a quad bank DRAM, 4 banks x 16Mb

addresses x 8 I/Os.

The device is designed to comply with DDR2 DRAM

key features such as posted CAS# with additive latency,

Write latency = Read latency -1 and On Die

Termination(ODT).

All of the control and address inputs are

synchronized with a pair of externally supplied

differential clocks. Inputs are latched at the cross point

of differential clocks (CK rising and CK# falling)

All I/Os are synchronized with a pair of bidirectional

strobes (DQS and DQS#) in a source synchronous

fashion. The address bus is used to convey row,

column, and bank address information in RAS #, CAS#

multiplexing style. Accesses begin with the registration

of a Bank Activate command, and then it is followed by

a Read or Write command. Read and write accesses to

the DDR2 SDRAM are 4 or 8-bit burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed

sequence.

Operating the four memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. An

auto precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end of

the burst sequence. A sequential and gapless data rate

is possible depending on burst length, CAS latency, and

speed grade of the device

Table 1. Ordering Information

Part Number

Clock Frequency

Data Rate

Power Supply

Package

AS4C64M8D2-25BCN

400MHz

800Mbps/pin

VDD 1.8V, VDDQ 1.8V

60 ball FBGA

AS4C64M8D2-25BIN

400MHz

800Mbps/pin

VDD 1.8V, VDDQ 1.8V

60 ball FBGA

B: indicates 60-ball 8 x 10 x 1.2mm (max) FBGA package

C: indicates commercial temperature

I: indicates industrial temperature

N: indicates Pb and Halogen Free - ROHS Compliant

Table 2. Speed Grade Information

Speed Grade

Clock Frequency

CAS Latency

tRCD (ns)

tRP (ns)

DDR2-800

400 MHz

5

12.5

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