AS4C64M8D2 datasheet(43/59 Pages) ALSC

43 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

Figure 28. Write burst interrupt timing: (CL=3, AL=0, RL=3, WL=2, BL=8)

CK#

CMD

NOP

Write A

NOP

Write B

NOP

DQS

DQS#

DQs

NOTE 1: Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

NOTE 2: Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or

Precharge command is prohibited.

NOTE 3: Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt

timings are prohibited.

NOTE 4: Write burst interruption is allowed to any bank inside DRAM.

NOTE 5: Write burst with Auto Precharge enabled is not allowed to interrupt.

NOTE 6: Write burst interruption is allowed by another Write with Auto Precharge command.

NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to actual

burst. For example, minimum Write to Precharge timing is WL + BL/2 + tWR where tWR starts with the rising clock after the

uninterrupted burst end and not from the end of actual burst end.

AS4C64M8D2 Datasheet(PDF) 43 Page - Alliance Semiconductor Corporation