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AS4C64M8D2 Datasheet(PDF) 24 Page - Alliance Semiconductor Corporation |
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AS4C64M8D2 Datasheet(HTML) 24 Page - Alliance Semiconductor Corporation |
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24 / 59 page  AS4C64M8D2 Confidential 24 Rev. 1.0 Feb. /2014 Table 25. Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 1.8V 0.1V, TOPER = 0~95C) Symbol Parameter -25 -3 Unit Specific Notes Min. Max. Min. Max. tCK(avg) Average clock period CL=3 5 8 5 8 ns 15, 33, 34 CL=4 3.75 8 3.75 8 ns 15, 33, 34 CL=5 2.5 8 3 8 ns 15, 33, 34 CL=6 2.5 8 - - ns 15, 33, 34 tCH(avg) Average clock HIGH pulse width 0.48 0.52 0.48 0.52 tCK 34, 35 tCL(avg) Average Clock LOW pulse width 0.48 0.52 0.48 0.52 tCK 34, 35 WL Write command to DQS associated clock edge RL-1 RL-1 tCK tDQSS DQS latching rising transitions to associated clock edges -0.25 0.25 -0.25 0.25 tCK 28 tDSS DQS falling edge to CK setup time 0.2 - 0.2 - tCK 28 tDSH DQS falling edge hold time from CK 0.2 - 0.2 - tCK tDQSH DQS input HIGH pulse width 0.35 - 0.35 - tCK tDQSL DQS input LOW pulse width 0.35 - 0.35 - tCK tWPRE Write preamble 0.35 - 0.35 - tCK tWPST Write postamble 0.4 0.6 0.4 0.6 tCK 10 tIS(base) Address and Control input setup time 0.175 - 0.2 - ns 5, 7, 9, 22, 27 tIH(base) Address and Control input hold time 0.25 - 0.275 - ns 5, 7, 9, 23, 27 tIPW Control & Address input pulse width for each input 0.6 - 0.6 - tCK tDS(base) DQ & DM input setup time 0.05 - 0.1 - ns 6, 7, 8, 20, 26, 29 tDH(base) DQ & DM input hold time 0.125 - 0.175 - ns 6, 7, 8, 21, 26, 29 tDIPW DQ and DM input pulse width for each input 0.35 - 0.35 - tCK tAC DQ output access time from CK, CK# -0.4 0.4 -0.45 0.45 ns 38 tDQSCK DQS output access time from CK, CK# -0.35 0.35 -0.4 0.4 ns 38 tHZ Data-out high-impedance time from CK, CK# - tAC(max) - tAC(max) ns 18, 38 tLZ(DQS) DQS(DQS#) low-impedance time from CK, CK# tAC(min) tAC(max) tAC(min) tAC(max) ns 18, 38 tLZ(DQ) DQ low-impedance time from CK, CK# 2tAC(min) tAC(max) 2tAC(min) tAC(max) ns 18, 38 tDQSQ DQS-DQ skew for DQS and associated DQ signals - 0.2 - 0.24 ns 13 tHP CK half pulse width min(tCL,tCH) - min(tCL,tCH) - ns 11, 12, 35 tQHS DQ hold skew factor - 0.3 - 0.34 ns 12, 36 tQH DQ/DQS output hold time from DQS tHP -tQHS - - tHP -tQHS ns 37 tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK 19, 39 tRPST Read postamble 0.4 0.6 0.4 0.6 tCK 19, 40 tRRD Active to active command period 10 - 10 - ns 4, 30 tCCD CAS# to CAS# command delay 2 - 2 - tCK tWR Write recovery time 15 - 15 - ns 30 tDAL Auto Power write recovery + precharge time WR + tRP - WR + tRP - ns 14, 31 tWTR Internal Write to Read Command Delay 7.5 - 7.5 - ns 3, 24, 30 tRTP Internal read to precharge command delay 7.5 - 7.5 - ns 3, 30 tCKE CKE minimum pulse width 3 - 3 - tCK 25 tXSNR Exit self refresh to non-read command delay tRFC+10 - tRFC+10 - ns 30 tXSRD Exit self refresh to a read command 200 - 200 - tCK tXP Exit precharge power down to any command 2 - 2 - tCK |
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