AS4C64M8D2 datasheet(33/59 Pages) ALSC

33 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

Timing Waveforms

Figure 7. Initialization sequence after power-up

CK#

tCH

CKE

Command

tCL

tIS

ODT

tIS

NOP

PRE

ALL

EMR

MRS

PRE

ALL

REF

MRS

EMR

ANY

CMD

400ns

tRP

tMRD

tRP

tMRD

Follow OCD Flowchart

tOIT

min 200 Cycle

DLL

ENABLE

DLL

RESET

OCD

Default

OCD

CAL.MOD

E EXIT

NOTE 1: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.

tRFC

Figure 8. ODT update delay timing-tMOD

EMRS

Updating

Rtt

tIS

NOP

CMD

tAOFD

tMOD, max

tMOD, min

Old setting

New setting

ODT

NOTE 1: To prevent any impedance glitch on the channel, the following conditions must be met:

- tAOFD must be met before issuing the EMRS command.

- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.

then the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned

on the ODT.

NOTE 2: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).

NOTE 3: "setting" in this diagram is the Register and I/O setting, not what is measured from outside.

CK#

Figure 9. ODT update delay timing-tMOD, as measured from outside

CK#

Rtt

tIS

EMRS

CMD

tAOFD

tMOD, max

Old setting

New setting

ODT

NOP

tAOND

NOTE 1: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).

NOTE 2: "setting" in this diagram is measured from outside.

AS4C64M8D2 Datasheet(PDF) 33 Page - Alliance Semiconductor Corporation

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