AS4C64M8D2 datasheet(26/59 Pages) ALSC

26 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

General notes, which may apply for all AC parameters:

NOTE 1: DDR2 SDRAM AC timing reference load

The below figure represents the timing reference load used in defining the relevant timing parameters of the part.

It is not intended to be either a precise representation of the typical system environment or a depiction of the actual

load presented by a production tester.

Figure 5. AC timing reference load

VDDQ

DUT

DQS

DQS#

VTT=VDDQ/2

25Ω

Timing reference

point

Ouput

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing

reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g.

DQS#) signal.

NOTE 2: Slew Rate Measurement Levels

a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single

ended signals. For differential signals (e.g. DQS – DQS#) output slew rate is measured between DQS – DQS#

= - 500 mV and DQS – DQS# = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily

tested on each device.

b) Input slew rate for single ended signals is measured from VREF (dc) to VIH (ac), min for rising edges and from

VREF(dc) to VIL(ac),max for falling edges. For differential signals (e.g. CK – CK#) slew rate for rising edges is

measured from CK – CK# = - 250 mV to CK -CK# = + 500 mV (+ 250 mV to - 500 mV for falling edges).

c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK#, or

between DQS and DQS# for differential strobe.

NOTE 3: DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as bellow

AS4C64M8D2 Datasheet(PDF) 26 Page - Alliance Semiconductor Corporation