R5F56519FDFP datasheet(129/190 Pages) RENESAS

129 / 190 page

R01DS0276EJ0100 Rev.1.00

Page 129 of 190

Aug 24, 2016

RX65N Group, RX651 Group

5. Electrical Characteristics

5.3.5

Bus Timing

Table 5.22

Bus Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit

Test Conditions

Address delay time

tAD

—

12.5

Figure 5.16 to

Figure 5.21

Byte control delay time

tBCD

—

12.5

CS# delay time

tCSD

—

12.5

ALE delay time

tALED

—

12.5

RD# delay time

tRSD

—

12.5

Read data setup time

tRDS

12.5

—

Read data hold time

tRDH

0—

WR# delay time

tWRD

—

12.5

Write data delay time

tWDD

—

12.5

Write data hold time

tWDH

0—

WAIT# setup time

tWTS

12.5

—

Figure 5.22

WAIT# hold time

tWTH

0—

Address delay time 2 (SDRAM)

tAD2

12.5

Figure 5.23

CS# delay time 2 (SDRAM)

tCSD2

12.5

DQM delay time (SDRAM)

tDQMD

12.5

CKE delay time (SDRAM)

tCKED

12.5

Read data setup time 2 (SDRAM)

tRDS2

—

Read data hold time 2 (SDRAM)

tRDH2

0—

Write data delay time 2 (SDRAM)

tWDD2

—

12.5

Write data hold time 2 (SDRAM)

tWDH2

1—

WE# delay time (SDRAM)

tWED

12.5

RAS# delay time (SDRAM)

tRASD

12.5

CAS# delay time (SDRAM)

tCASD

12.5

R5F56519FDFP Datasheet(PDF) 129 Page - Renesas Technology Corp

R5F56519FDFP Datasheet(HTML) 129 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL