CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 25 of 58
Note:
3.
I2C-compatible function must be separately enabled, as described in Section 13.0.
Bits [7,1:0] of the HAPI/I2C Configuration Register control the pin out configuration of the HAPI and I2C-compatible interfaces.
Bits [5:2] are used in HAPI mode only, and are described in Section 14.0. Table 12-1 shows the HAPI port configurations, and
Table 12-2 shows I2C pin location configuration options. These I2C-compatible options exist due to pin limitations in certain
packages, and to allow simultaneous HAPI and I2C-compatible operation.
HAPI operation is enabled whenever either HAPI Port Width Bit (Bit 1 or 0) is non-zero. This affects GPIO operation as described
in Section 14.0. The I2C-compatible interface must be separately enabled as described in Section13.0.
13.0
I2C-compatible Controller
The I2C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and
multi-master modes of operation. The I2C-compatible block functions by handling the low-level signaling in hardware, and issuing
interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the
hardware keeps the I2C-compatible bus idle if necessary.
The I2C-compatible interface generates an interrupt to the microcontroller at the end of each received or transmitted byte, when
a stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given
in Section 16.9.
The I2C-compatible interface consists of two registers, an I2C Data Register (Figure 13-1) and an I2C Status and Control Register
(Figure 13-2). The Data Register is implemented as separate read and write registers. Generally, the I2C Status and Control
Register should only be monitored after the I2C interrupt, as all bits are valid at that time. Polling this register at other times could
read misleading bit status if a transaction is underway.
The I2C SCL clock is connected to bit 0 of GPIO port 1 or GPIO port 2, and the I2C SDA data is connected to bit 1 of GPIO port
1 or GPIO port 2. Refer to Section 12.0 for the bit definitions and functionality of the HAPI/I2C Configuration Register, which is
used to set the locations of the configurable I2C pins. Once the I2C-compatible functionality is enabled by setting bit 0 of the I2C
Status & Control Register, the two LSB ([1:0]) of the corresponding GPIO port is placed in Open Drain mode, regardless of the
settings of the GPIO Configuration Register. The electrical characteristics of the I2C-compatible interface is the same as that of
GPIO ports 1 and 2. Note that the IOL (max) is 2 mA @ VOL = 2.0V for ports 1 and 2.
All control of the I2C clock and data lines is performed by the I2C-compatible block.
I2C Data
ADDRESS 0x29
Bits [7..0] : I2C Data
Contains 8-bit data on the I2C Bus.
I2C Status and Control
ADDRESS 0x28
Reset
0
000
000
0
Table 12-1. HAPI Port Configuration
Port Width (Bit 0 and 1, Figure 12-1)
HAPI Port Width
11
24 Bits: P3[7:0], P1[7:0], P0[7:0]
10
16 Bits: P1[7:0], P0[7:0]
01
8 Bits: P0[7:0]
00
No HAPI Interface
Table 12-2. I2C Port Configuration
I2C Position (Bit 7, Figure 12-1)I2C Port Width (Bit 1, Figure 12-1)
I2C Position
Don’t Care
1
I2C on P2[1:0], 0:SCL, 1:SDA
00
I2C on P1[1:0], 0:SCL, 1:SDA
10
I2C on P2[1:0], 0:SCL, 1:SDA
Bit #
7
654
321
0
Bit Name
I2C Data 7
I2C Data 6
I2C Data 5
I2C Data 4
I2C Data 3
I2C Data 2
I2C Data 1
I2C Data 0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
X
XXX
XXX
X
Figure 13-1. I2C Data Register
Bit #
7
654
321
0
Figure 13-2. I2C Status and Control Register
Figure 12-1. HAPI/I2C Configuration Register
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