AD9689-2000EBZ datasheet(28/134 Pages) AD

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AD9689

Data Sheet

Rev. A | Page 28 of 134

THEORY OF OPERATION

The AD9689 has two analog input channels and up to eight

JESD204B output lane pairs. The ADC samples wide bandwidth

analog signals of up to 5 GHz. The actual −3 dB roll-off of the

analog inputs is 9 GHz. The AD9689 is optimized for wide input

bandwidth, high sampling rate, excellent linearity, and low

power in a small package.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations.

The AD9689 has several functions that simplify the AGC

function in a communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect output bits of the ADC. If the input

signal level exceeds the programmable threshold, the fast detect

indicator goes high. Because this threshold indicator has low

latency, the user can quickly turn down the system gain to avoid

an overrange condition at the ADC input.

The Subclass 1 JESD204B-based high speed serialized output data

lanes can be configured in one-lane (L = 1), two-lane (L = 2),

four-lane (L = 4), and eight-lane (L = 8) configurations, depending

on the sample rate and the decimation ratio. Multiple device

synchronization is supported through the SYSREF± and

SYNCINB± input pins. The SYSREF± pin in the AD9689 can

also be used as a timestamp of data as it passes through the

ADC and out of the JESD204B interface.

ADC ARCHITECTURE

The architecture of the AD9689 consists of an input buffered

pipelined ADC. The input buffer provides a termination

impedance to the analog input signal. This termination

impedance is set to 200 Ω. The equivalent circuit diagram of the

analog input termination is shown in Figure 66. The input

buffer is optimized for high linearity, low noise, and low power

across a wide bandwidth.

The input buffer provides a linear high input impedance

(for ease of drive) and reduces kickback from the ADC. The

quantized outputs from each stage are combined into a final

14-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate with a new input

sample; at the same time, the remaining stages operate with the

preceding samples. Sampling occurs on the rising edge of the clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9689 is a differential buffer. The internal

common-mode voltage of the buffer is 1.4 V. The clock signal

alternately switches the input circuit between sample mode and

hold mode.

Either a differential capacitor or two single-ended capacitors (or

a combination of both) can be placed on the inputs to provide a

matching passive network. These capacitors ultimately create a

low-pass filter that limits unwanted broadband noise. For more

information, refer to the Analog Dialogue article, “Transformer-

Coupled Front-End for Wideband A/D Converters” (Volume 39,

April 2005). In general, the precise front-end network

component values depend on the application.

Figure 78 shows the differential input return loss curve for the

analog inputs across a frequency range of 100 MHz to 10 GHz.

The reference impedance is 100 Ω.

5.0

–5.0

2.0

1.0

–1.0

FREQUENCY (100MHz TO 10GHz)

–2.0

0.5

–0.5

0.2

–0.2

FREQUENCY = 100MHz

SDD11 = 0.301/–8.069

IMPEDANCE = Z0 × (1.838 – j0.171)

FREQUENCY = 1GHz

SDD11 = 0.352/–73.534

IMPEDANCE = Z0 × (0.947 – j0.731)

FREQUENCY = 3GHz

SDD11 = 0.496/175.045

IMPEDANCE = Z0 × (0.337 – j0.038)

FREQUENCY = 4GHz

SDD11 = 0.500/136.667

IMPEDANCE = Z0 × (0.379 + j0.347)

FREQUENCY = 5GHz

SDD11 = 0.475/79.360

IMPEDANCE = Z0 × (0.737 + j0.889)

Figure 78. Differential Input Return Loss

For best dynamic performance, the source impedances driving

VIN+x and VIN−x must be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference

buffer creates a differential reference that defines the span of the

ADC core.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. For the AD9689,

the available span is programmable through the SPI port from

1.13 V p-p to 2.04 V p-p differential, with 1.7 V p-p differential

being the default.

AD9689-2000EBZ Datasheet(PDF) 28 Page - Analog Devices

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