AD9689-2000EBZ datasheet(99/134 Pages) AD

99 / 134 page

Data Sheet

AD9689

Rev. A | Page 99 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x000A Scratch pad

[7:0] Scratch pad

Chip scratch pad register. This register is used to provide a

consistent memory location for software debug.

0x0

R/W

0x000B SPI revision

[7:0] SPI revision

SPI revision register. 0x01: Revision 1.0.

0x1

00000001 Revision 1.0.

0x000C Vendor ID LSB

[7:0] Vendor ID LSB

Vendor ID[7:0].

0x56

0x000D Vendor ID MSB

[7:0] Vendor ID MSB

Vendor ID[15:8].

0x04

0x000F Transfer

[7:1] Reserved

Reserved.

0x0

Chip transfer

Self clearing chip transfer bit. This bit is used to update the

DDC FTW/POW/MAW/MBW increment and phase offset

registers when DDC phase update mode (Register 0x0300, Bit

7) = 1, which makes it possible to synchronously update the

DDC mixer frequencies. This bit is also used to update the

coefficients for the programmable filter (PFILT).

0x0

R/W

Do nothing. Bit is only cleared after transfer is complete.

Self clearing bit used to synchronize the transfer of data from

master to slave registers.

Clock/SYSREF/Chip Power-Down Pin Control Registers

Table 47.

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x003F Chip PDWN pin

(local)

Local chip PDWN pin

disable

Function is determined by Register 0x0040, Bits[7:6].

0x0

R/W

Power-down pin (PDWN/STBY) enabled (default).

Power-down pin (PDWN/STBY) disabled/ignored.

[6:0] Reserved

Reserved.

0x0

0x0040 Chip Pin Control 1

[7:6] Chip PDWN pin

functionality

External power-down pin functionality. Assertion of the external

power-down pin (PDWN/STBY) has higher priority than the channel

power mode bits (Register 0x0002, Bits[1:0]). The PDWN/

STBY pin is only used when Register 0x0040, Bits[7:6] = 00 or 01.

0x0

R/W

Power-down pin (default). Assertion of external power-down pin

(PDWN/STBY) causes the chip to enter full power-down mode.

Standby pin. Assertion of external power-down pin (PDWN/STBY)

causes the chip to enter standby mode.

Pin disabled. Power-down pin (PDWN/STBY) is ignored.

[5:3] Chip FD_B/GPIO_B0 pin

functionality

Fast Detect B/GPIO B0 pin functionality.

0x7

R/W

000

Fast Detect B output.

001

JESD204B LMFC output.

110

Pin functionality determined by Register 0x0041, Bits[7:4].

111

Disabled. Configured as input with weak pull-down (default).

[2:0] Chip FD_A/GPIO_A0 pin

functionality

Fast Detect A/GPIO A0 pin functionality.

0x7

R/W

000

Fast Detect A output.

001

JESD204B LMFC output.

110

Pin functionality determined by Register 0x0041, Bits[3:0].

111

Disabled. Configured as an input with weak pull-down (default).

0x0041 Chip Pin Control 2

[7:4] Chip FD_B/GPIO_B0 pin

secondary functionality

Fast Detect B/GPIO B0 pin secondary functionality (only used

when Register 0x0040, Bits[5:3] = 110).

0x0

R/W

0000

Chip GPIO B0 input (NCO channel selection).

0001

Chip transfer input.

1000

Master next trigger output (MNTO).

1001

Slave next trigger input (SNTI).

[3:0] Chip FD_A/GPIO_A0 pin

secondary functionality

Fast Detect A/GPIO B0 pin secondary functionality (only used

when Register 0x0040, Bits[2:0] = 110).

0x0

R/W

0000

Chip GPIO A0 input (NCO channel selection).

0001

Chip transfer input.

1000

Master next trigger output (MNTO).

1001

Slave next trigger input (SNTI).

AD9689-2000EBZ Datasheet(PDF) 99 Page - Analog Devices

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