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AD9689-2000EBZ Datasheet(PDF) 100 Page - Analog Devices |
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AD9689-2000EBZ Datasheet(HTML) 100 Page - Analog Devices |
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100 / 134 page  AD9689 Data Sheet Rev. A | Page 100 of 134 Addr. Name Bit(s) Bit Name Setting Description Reset Access 0x0042 Chip Pin Control 3 [7:4] Chip GPIO_B1 pin functionality GPIO B1 pin functionality. 0xF R/W 0000 Chip GPIO B1 input (NCO channel selection). 1000 Master next trigger output (MNTO). 1001 Slave next trigger input (SNTI). 1111 Disabled (configured as input with weak pull-down). [3:0] Chip GPIO_B1 pin functionality GPIO A1 pin functionality. 0xF R/W 0000 Chip GPIO A1 input (NCO channel selection). 1000 Master next trigger output (MNTO). 1001 Slave next trigger input (SNTI). 1111 Disabled (configured as input with weak pull-down). 0x0108 Clock divider control [7:3] Reserved Reserved. 0x0 R [2:0] Input clock divider (CLK± pins) 0x0 R/W 00 Divide by 1. 01 Divide by 2. 11 Divide by 4. 0x0109 Clock divider phase (local) [7:4] Reserved Reserved. 0x0 R [3:0] Clock divider phase offset 0x0 R/W 0000 0 input clock cycles delayed. 0001 ½ input clock cycles delayed (invert clock). 0010 1 input clock cycles delayed. … … 1110 7 input clock cycles delayed. 1111 7½ input clock cycles delayed. 0x010A Clock divider and SYSREF control 7 Clock divider auto phase adjust enable Clock divider auto phase adjust enable. When enabled, Register 0x0129, Bits[3:0] contain the phase of the divider when SYSREF was captured. The actual divider phase offset = Register 0x0129, Bits[3:0] + Register 0x0109, Bits[3:0]. 0x0 R/W 0 Clock divider phase is not changed by SYSREF (disabled). 1 Clock divider phase is automatically adjusted by SYSREF (enabled). [6:4] Reserved Reserved. 0x0 R [3:2] Clock divider negative skew window Clock divider negative skew window (measured in ½ input device clocks). Number of ½ clock cycles before the input device clock by which captured SYSREF transitions are ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]. The skew allows some uncertainty in the sampling of SYSREF without disturbing the input clock divider. Also, SYSREF must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. 0x0 R/W 00 No negative skew; SYSREF must be captured accurately. 01 ½ device clock of negative skew. 10 1 device clocks of negative skew. 11 1½ device clocks of negative skew. [1:0] Clock divider positive skew window Clock divider positive skew window (measured in ½ input device clocks). Number of clock cycles after the input device clock by which captured SYSREF transitions are ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]. The skew allows some uncertainty in the sampling of SYSREF without disturbing the input clock divider. Also, SYSREF must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. 0x0 R/W 00 No positive skew; SYSREF must be captured accurately. 01 ½ device clock of positive skew. 10 1 device clocks of positive skew. 11 1½ device clocks of positive skew. |
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