AD9689-2000EBZ datasheet(104/134 Pages) AD

104 / 134 page

AD9689

Data Sheet

Rev. A | Page 104 of 134

Fast Detect and Signal Monitor Control Registers

Table 49.

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x0245 Fast detect control

(local)

[7:4] Reserved

Reserved.

0x0

Force FD_A/FD_B pins

0x0

R/W

Normal operation of the fast detect pin.

Force a value on the fast detect pin (see Bit 2).

Force value of

FD_A/FD_B pins

The fast detect output pin for this channel is set to this value

when the output is forced.

0x0

R/W

Reserved

Reserved.

0x0

Enable fast detect output

0x0

R/W

Fast detect disabled.

Fast detect enabled.

0x0247 Fast detect up LSB

(local)

[7:0] Fast detect upper

threshold

LSBs of fast detect upper threshold. This register contains the

8 LSBs of the programmable 13-bit upper threshold that is

compared to the fine ADC magnitude.

0x0

R/W

0x0248 Fast detect up MSB

(local)

[7:5] Reserved

Reserved.

0x0

[4:0] Fast detect upper

threshold

LSBs of fast detect upper threshold. This register contains the

8 LSBS of the programmable 13-bit upper threshold that is

compared to the fine ADC magnitude.

0x0

R/W

0x0249 Fast detect low LSB

(local)

[7:0] Fast detect lower

threshold

LSBs of fast detect lower threshold. This register contains the

8 LSBS of the programmable 13-bit lower threshold that is

compared to the fine ADC magnitude.

0x0

R/W

0x024A Fast detect low

MSB (local)

[7:5] Reserved

Reserved.

0x0

[4:0] Fast detect lower

threshold

LSBs of fast detect lower threshold. This register contains the

8 LSBs of the programmable 13-bit lower threshold that is

compared to the fine ADC magnitude.

0x0

R/W

0x024B Fast detect dwell

LSB (local)

[7:0] Fast detect dwell time

LSBs of fast detect dwell time counter target. This is a load

value for a 16-bit counter that determines how long the ADC

data must remain below the lower threshold before the

FD_x pins are reset to 0.

0x0

R/W

0x024C Fast detect dwell

MSB (local)

[7:0] Fast detect dwell time

LSBs of fast detect dwell time counter target. This is a load

value for a 16-bit counter that determines how long the ADC

data must remain below the lower threshold before the

FD_x pins are reset to 0.

0x0

R/W

0x026F Signal monitor

sync control

[7:2] Reserved

Reserved.

0x0

Signal monitor next

synchronization mode

Signal monitor next synchronization mode.

0x0

R/W

Continuous mode.

Next synchronization mode. Only the next valid edge of the

SYSREF± pin is used to synchronize the signal monitor block.

Subsequent edges of the SYSREF± pin are ignored. When the

next SYSREF has been captured, Register 0x026F, Bit 0 is cleared.

The SYSREF± pin must be an integer multiple of the signal monitor

period for this function to operate correctly in continuous mode.

Signal monitor

synchronization mode

Signal monitor synchronization enable.

0x0

R/W

Synchronization disabled.

If Register 0x026F, Bit 1 = 1, only the next valid edge of the

SYSREF± pin is used to synchronize the signal monitor block.

Subsequent edges of the SYSREF± pin are ignored. When the

next SYSREF signal is received, this bit is cleared. The SYSREF±

input pin must be enabled to synchronize the signal monitor

blocks.

0x0270 Signal monitor

control (local)

[7:2] Reserved

Reserved.

0x0

Peak detector

0x0

R/W

Peak detector disabled.

Peak detector enabled.

Reserved

Reserved.

0x0

AD9689-2000EBZ Datasheet(PDF) 104 Page - Analog Devices

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