SLG46121V datasheet(43/98 Pages) DIALOG

43 / 98 page

000-0046121--106

Page 42 of 97

SLG46121

10.1.2 2-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings

Table 28. DFF0 Register Settings

Signal Function

Address

DFF0 or Latch

select

reg <396>

0: DFF function

1: Latch function

DFF0 output select

reg <397>

0: Q output

1: nQ output

DFF0 initial polarity

select

reg <398>

0: Low

1: High

LUT2_0 data

reg <399:396>

LUT2_0 data

LUT2_0 or DFF0

select

reg <420>

0: LUT2_0

1: DFF0

Table 29. DFF1 Register Settings

Signal Function

Address

DFF1 or Latch

select

reg <400>

0: DFF function

1: Latch function

DFF1 output select

reg <401>

0: Q output

1: nQ output

DFF1 initial polarity

select

reg <402>

0: Low

1: High

LUT2_1 data

reg <403:400>

LUT2_1 data

LUT2_1 or DFF1

select

reg <421>

0: LUT2_1

1: DFF1

Table 30. DFF2 Register Settings

Signal Function

Address

DFF2 or Latch

select

reg <404>

0: DFF function

1: Latch function

DFF2 output select

reg <405>

0: Q output

1: nQ output

DFF2 initial polarity

select

reg <406>

0: Low

1: High

LUT2_2 data

reg <407:404>

LUT2_2 data

LUT2_2 or DFF2

select

reg <422>

0: LUT2_2

1: DFF2

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