SLG46121V datasheet(48/98 Pages) DIALOG

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000-0046121--106

Page 47 of 97

SLG46121

10.2.2 3-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings

Table 36. DFF4 Register Settings

Signal Function

Address

DFF4 or Latch

select

reg <424>

0: DFF function

1: Latch function

DFF4 output select

reg <425>

0: Q output

1: nQ output

DFF4 rstb/setb

Select

reg <426>

1: setb from matrix out

0: resetb from matrix out

DFF4 initial polarity

select

reg <427>

0: Low

1: High

LUT3_0 data

reg <431:424>

LUT3_0 data

LUT3_0 or DFF4

select

reg <496>

0: LUT3_0

1: DFF4

Table 37. DFF5 Register Settings

Signal Function

Address

DFF5 or Latch

Select

reg <432>

0: DFF function

1: Latch function

DFF5 Output Select

reg <433>

0: Q output

1: nQ output

DFF5 rstb/setb

Select

reg <434>

1: setb from matrix out

0: resetb from matrix out

DFF5 initial polarity

select

reg <435>

0: Low

1: High

LUT3_1 data

reg <439:432>

LUT3_1 data

LUT3_1 or DFF5

select

reg <497>

0: LUT3_1

1: DFF5

Table 38. DFF6 Register Settings

Signal Function

Address

DFF6 or Latch

select

reg <440>

0: DFF function

1: Latch function

DFF6 output select

reg <441>

0: Q output

1: nQ output

DFF6 rstb/setb

Select

reg <442>

1: setb from matrix out

0: resetb from matrix out

DFF6 initial polarity

select

reg <443>

0: Low

1: High

LUT3_2 data

reg <447:440>

LUT3_2 data

LUT3_2 or DFF6

select

reg <498>

0: LUT3_2

1: DFF6

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