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SLG46121V Datasheet(PDF) 15 Page - Dialog Semiconductor

Part # SLG46121V
Description  Personal Computers and Servers
PDF  98 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

SLG46121V Datasheet(HTML) 15 Page - Dialog Semiconductor

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Page 14 of 97
SLG46121
5.8 IDD Estimator
5.9 Timing Estimator
Table 1. Typical Current estimated for each macrocell.
Symbol
Parameter
Note
VDD = 1.8V
VDD = 3.3V
VDD = 5.0V
Unit
I
Current
Chip Quiescent
0.5
0.8
1.0
A
Vref
55.7
56.0
62.5
A
Vref Buffer (each)
0.6
14.1
14.6
A
OSC 25 kHz, predivide = 1
3.1
4.7
6.4
A
OSC 25 kHz, predivide = 8
3.0
4.3
5.8
A
OSC 2 MHz, predivide = 1
29.3
51.0
79.8
A
OSC 2 MHz, predivide = 8
17.4
23.2
29.0
A
1st ACMP used (includes Vref)
59.6
60.0
66.5
A
Each additional ACMP add
3.9
4.0
4.0
A
Table 2. Typical Delay estimated for each macrocell.
Symbol Parameter
Note
VDD/VDD2 =
1.8V
VDD/VDD2 =
3.3V
VDD/VDD2 =
5.0V
Unit
rising falling rising falling rising falling
tpd
Delay
Digital Input without Schmitt Trigger --
Push Pull
44.2
43.5
17.8
18.2
12.7
13.0
ns
tpd
Delay
Digital Input with Schmitt Trigger -- Push
Pull
43.3
42.5
17.7
18.0
12.6
13.0
ns
tpd
Delay
Low Voltage Digital input -- Push Pull
45.6
517.0
18.1
215.3
12.7
144.9
ns
tpd
Delay
Digital Input without Schmitt Trigger --
NMOS
—
83.8
—
29.9
—
19.5
ns
tpd
Delay
Output enable from pin, OE Hi-Z to 1
44.8
—
17.9
—
12.6
—
ns
tpd
Delay
Output enable from pin, OE Hi-Z to 0
43.4
17.7
12.8
ns
tpd
Delay
2-bit LUT
18.7
22.1
8.0
8.7
5.8
6.0
ns
tpd
Delay
Latch (2-bit LUT shared macrocell
inputs)
26.5
30.8
11.3
12.3
8.1
8.5
ns
tpd
Delay
3-bit LUT
21.3
24.4
9.1
9.6
6.5
6.6
ns
tpd
Delay
3-bit LUT (LATCH shared macrocell
inputs)
26.8
25.4
11.2
10.2
8.0
7.1
ns
tpd
Delay
Latch with nRST/nSET (3-bit LUT
shared macrocell inputs)
29.7
34.7
12.6
13.9
9.1
9.6
ns
tpd
Delay
4-bit LUT (shared macrocell inputs)
34.0
32.6
14.4
13.0
10.3
9.1
ns
tpd
Delay
2-bit LUT (Latch shared macrocell
inputs)
26.8
25.4
11.2
10.2
8.0
7.1
ns
tpd
Delay
CNT/DLY
44.2
38.8
18.7
16.4
13.3
11.8
ns
tpd
Delay
CNT/DLY (shared macrocell inputs)
43.2
39.7
18.4
16.8
13.0
12.1
ns
tpd
Delay
CNT3/DLY3 Rising Edge Detect (shared
macrocell inputs)
38.2
—
16.0
—
11.4
—
ns
tpd
Delay
CNT3/DLY3 Falling Edge Detect
(shared macrocell inputs)
—
40.4
—
16.4
—
11.6
ns
tpd
Delay
CNT3/DLY3 Both Edge Detect (shared
macrocell inputs)
38.2
40.5
15.9
16.5
11.3
11.5
ns
tpd
Delay
Filter
191.6
193
77.4
77.8
50.7
52.1
ns



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