SLG46121V datasheet(35/98 Pages) DIALOG

35 / 98 page

000-0046121--106

Page 34 of 97

SLG46121

reg <233:228>

in0 of LUT3_7

reg <239:234>

in1 of LUT3_7

reg <245:240>

in2 of LUT3_7

reg <251:246>

in0 of LUT3_8 (Input of pipe delay)

reg <257:252>

in1 of LUT3_8 (Resetb of pipe delay)

reg <263:258>

in2 of LUT3_8 (Clock of pipe delay)

reg <269:264>

in0 of LUT4_0 (Input for Delay2 ext. clock or Counter2 8bit external Clock)

reg <275:270>

in1 of LUT4_0 (Input for delay2 or counter2 reset input)

reg <281:276>

in2 of LUT4_0

reg <287:282>

in3 of LUT4_0

reg <293:288>

in0 of LUT4_1 (Input for Delay3 ext. clock or Counter3 8bit external Clock)

reg <299:294>

in1 of LUT4_1 (Input for delay3 or counter3 reset input)

reg <305:300>

in2 of LUT4_1

reg <311:306>

in3 of LUT4_1

reg <317:312>

Input for delay0 or counter0 (14bits) external clock

reg <323:318>

Input for Delay1 ext. clock or Counter1 8bit external Clock

reg <329:324>

Input for delay1 or counter1 reset input

reg <335:330>

Not used

reg <341:336>

pdb for ACMP0

reg <347:342>

pdb for ACMP1

reg <353:348>

Input for programmable delay for edge detector (Deglitch filter input)

reg <359:354>

Power down for osc. (higher priority) (high = power down).

reg <365:360>

Pin 8 digital out source

reg <371:366>

Pin 9 digital out source

reg <377:372>

Pin 10 digital out source

reg <383:378>

Pin 10 output enable

Table 16. Matrix Output Table

Address

Matrix Output Signal Function

Matrix Output

Number

SLG46121V Datasheet(PDF) 35 Page - Dialog Semiconductor

SLG46121V Datasheet(HTML) 35 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Datasheet Download

Link URL